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Host Pipes IP Authoring Flow
The prototype implementation of host pipes is intended to use a two-part compilation flow to generate your IP. To simulate your IP using a SYCL* program testbench, compile your full SYCL* program as follows:
icpx -fsycl -fintelfpga -Xssimulation -Xstarget=<FPGA device family or part number> <source.cpp>
The simulation flow uses additional “helper” kernels to connect the host pipes from each kernel to the host part of the program. In the reports generated by the compiler, you can identify your IP by the name you have given it in your SYCL* program.
When you have verified the functionality of your IP authoring kernel, you can generate RTL for your IP with the following compile command:
icpx -fsycl -fintelfpga -Xshardware -fsycl-device-code-split=per_kernel -Xstarget=<FPGA device family or part number> <source.cpp>
This command generates a separate project directory in your current working directory for each of your IPs, and directories for the “helper” kernels that you can ignore.
You can identify these directories by the extension .prj, with each subsequent kernel appending _<#> to the project directory, where <#> is an incrementing integer. For example, when compiling a source program named main, project directories are named main.prj, main_1.prj, main_2.prj, and so on.
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