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Debug During Verification
By default, the compiler instructs the simulator not to log any signals because logging signals slows the simulation, and waveform files can be extremely large. However, you can configure the compiler to save these waveforms for debugging purposes.
To enable signal logging in the simulator, invoke the icpx -fsycl command with the -Xsghdl option command as follows:
icpx -fsycl -fintelfpga -Xssimulation -Xstarget=<family_or_part_number> -Xsghdl <input files>
When the simulation finishes, open the vsim.wlf file inside the current directory to view the waveform.
To view the waveform after the simulation finishes:
In the Questa® simulator, open the vsim.wlf file inside the <project name>.prj directory.
Right-click the <IP_component_name>_inst block and select Add Wave.
You can now view the top-level component signals: start, done, ready_in, ready_out, parameters, and outputs. Use the waveform to see how the component interacts with its interfaces.TIP:When you view the simulation waveform in the Questa® simulator, the simulation clock period is set to a default value of 1000 picoseconds (ps). To synchronize the Time axis to show one cycle per tick mark, change the time resolution from picoseconds (ps) to nanoseconds (ns):
Right-click the timeline and select Grid, Timeline & Cursor Control.
Under Timeline Configuration, set the Time units to ns.
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