Intel® oneAPI DPC++ FPGA Optimization Guide

Developer Guide

Contents

Pipes Extension

Using global memory to communicate data between your kernels can constrain the performance of your design.
DPC++
 pipes provide a mechanism for passing data between kernels and synchronizing kernels with high efficiency and low latency.
DPC++
 pipes allow kernels to use on-device FIFO buffers to communicate directly with each other. The memory model of pipes allows them to be used for inter-kernel communication without waiting for kernel completion or involvement of the host processor, as shown in the following figure:
Using DPC++ Pipes to Decouple Data Movement between Concurrently Executing Kernels
Using DPC++ Pipes to Decouple Data Movement between Concurrently Executing Kernels

Product and Performance Information

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Performance varies by use, configuration and other factors. Learn more at www.Intel.com/PerformanceIndex.