External Memory Interfaces (EMIF) IP User Guide: Agilex™ 5 FPGAs and SoCs

ID 817467
Date 3/31/2025
Public
Document Table of Contents

4.4.14. s1_axi4lite_clock for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR5

Clock for sideband interface (secondary I/O bank).

Table 105.  Interface: s1_axi4lite_clockInterface type: clock
Port Name Direction Description
s1_axi4lite_clock Input Axi-Lite clock, to secondary IOSSM.