External Memory Interfaces (EMIF) IP User Guide: Agilex™ 5 FPGAs and SoCs

ID 817467
Date 3/31/2025
Public
Document Table of Contents

4.3.22. mem_ck_2 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR4

Clock pin to the memory (channel 2).

Table 82.  Interface: mem_ck_2Interface type: conduit
Port Name Direction Description
mem_2_ck_t Output CK Clock (true) channel 2.
mem_2_ck_c Output CK Clock (complement) channel 2.