External Memory Interfaces (EMIF) IP User Guide: Agilex™ 5 FPGAs and SoCs

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ID 817467
Date 3/31/2025
Public
Document Table of Contents
Document Table of Contents x
1. About the External Memory Interfaces Agilex™ 5 FPGA IP 2. Agilex™ 5 FPGA EMIF IP – Introduction 3. Agilex™ 5 FPGA EMIF IP – Product Architecture 4. Agilex™ 5 FPGA EMIF IP – End-User Signals 5. Agilex™ 5 FPGA EMIF IP – Simulating Memory IP 6. Agilex™ 5 FPGA EMIF IP - DDR4 Support 7. Agilex™ 5 FPGA EMIF IP - DDR5 Support 8. Agilex™ 5 FPGA EMIF IP - LPDDR4 Support 9. Agilex™ 5 FPGA EMIF IP - LPDDR5 Support 10. Agilex™ 5 FPGA EMIF IP – Timing Closure 11. Agilex™ 5 FPGA EMIF IP – Controller Optimization 12. Agilex™ 5 FPGA EMIF IP – Debugging 13. Agilex™ 5 FPGA EMIF IP - Mailbox Support 14. Document Revision History for External Memory Interfaces (EMIF) IP User Guide
1. About the External Memory Interfaces Agilex™ 5 FPGA IP x
1.1. Release Information
2. Agilex™ 5 FPGA EMIF IP – Introduction x
2.1. Agilex™ 5 EMIF IP Protocol and Feature Support 2.2. Agilex™ 5 EMIF IP Design Flow
2.2. Agilex™ 5 EMIF IP Design Flow x
2.2.1. Agilex™ 5 EMIF IP Design Checklist
3. Agilex™ 5 FPGA EMIF IP – Product Architecture x
3.1. Agilex™ 5 EMIF Architecture: Protocol and Maximum Interface Width Support 3.2. Agilex™ 5 EMIF Architecture: Introduction 3.3. Agilex™ 5 EMIF Sequencer 3.4. Agilex™ 5 EMIF Controller 3.5. Agilex™ 5 EMIF IP for Hard Processor Subsystem (HPS)
3.2. Agilex™ 5 EMIF Architecture: Introduction x
3.2.1. Agilex™ 5 EMIF Architecture: I/O Subsystem 3.2.2. Agilex™ 5 EMIF Architecture: I/O SSM 3.2.3. Agilex™ 5 EMIF Architecture: HSIO Bank 3.2.4. Agilex™ 5 EMIF Architecture: I/O Lane 3.2.5. Agilex™ 5 EMIF Architecture: Input DQS Clock Tree 3.2.6. Agilex™ 5 EMIF Architecture: PHY Clock Tree 3.2.7. Agilex™ 5 EMIF Architecture: PLL Reference Clock Networks 3.2.8. Agilex™ 5 EMIF Architecture: Clock Phase Alignment 3.2.9. User Clock in Different Core Access Modes
3.2.3. Agilex™ 5 EMIF Architecture: HSIO Bank x
3.2.3.1. Lockstep Configuration 3.2.3.2. Pin Placement 3.2.3.3. HSIO Sub-Bank Usage
3.4. Agilex™ 5 EMIF Controller x
3.4.1. Hard Memory Controller
3.4.1. Hard Memory Controller x
3.4.1.1. Hard Memory Controller Features
3.5. Agilex™ 5 EMIF IP for Hard Processor Subsystem (HPS) x
3.5.1. Restrictions on I/O Bank Usage for EMIF IP with HPS 3.5.2. Using the Legacy EMIF Debug Toolkit with Agilex 5 HPS Interfaces
4. Agilex™ 5 FPGA EMIF IP – End-User Signals x
4.1. IP Interfaces for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - DDR4 Component 4.2. IP Interfaces for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - DDR5 Component 4.3. IP Interfaces for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR4 4.4. IP Interfaces for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR5
4.1. IP Interfaces for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - DDR4 Component x
4.1.1. s0_axi4_clock_in for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - DDR4 Component 4.1.2. s0_axi4_clock_out for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - DDR4 Component 4.1.3. s0_axi4_ctrl_ready for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - DDR4 Component 4.1.4. core_init_n for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - DDR4 Component 4.1.5. s0_axi4 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - DDR4 Component 4.1.6. s0_axi4lite_clock for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - DDR4 Component 4.1.7. s0_axi4lite_reset_n for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - DDR4 Component 4.1.8. s0_axi4lite for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - DDR4 Component 4.1.9. mem_0 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - DDR4 Component 4.1.10. mem_ck_0 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - DDR4 Component 4.1.11. mem_reset_n for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - DDR4 Component 4.1.12. oct_0 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - DDR4 Component 4.1.13. ref_clk for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - DDR4 Component
4.2. IP Interfaces for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - DDR5 Component x
4.2.1. s0_axi4_clock_in for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - DDR5 Component 4.2.2. s0_axi4_clock_out for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - DDR5 Component 4.2.3. s0_axi4_ctrl_ready for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - DDR5 Component 4.2.4. core_init_n for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - DDR5 Component 4.2.5. s0_axi4 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - DDR5 Component 4.2.6. s1_axi4 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - DDR5 Component 4.2.7. s0_axi4lite_clock for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - DDR5 Component 4.2.8. s0_axi4lite_reset_n for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - DDR5 Component 4.2.9. s0_axi4lite for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - DDR5 Component 4.2.10. mem_0 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - DDR5 Component 4.2.11. mem_ck_0 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - DDR5 Component 4.2.12. mem_reset_n_0 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - DDR5 Component 4.2.13. mem_1 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - DDR5 Component 4.2.14. mem_ck_1 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - DDR5 Component 4.2.15. mem_reset_n_1 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - DDR5 Component 4.2.16. oct_0 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - DDR5 Component 4.2.17. oct_1 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - DDR5 Component 4.2.18. ref_clk for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - DDR5 Component
4.3. IP Interfaces for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR4 x
4.3.1. s0_axi4_clock_in for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR4 4.3.2. core_init_n for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR4 4.3.3. s0_axi4_ctrl_ready for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR4 4.3.4. s0_axi4_clock_out for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR4 4.3.5. s1_axi4_ctrl_ready for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR4 4.3.6. s1_axi4_clock_out for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR4 4.3.7. s0_axi4 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR4 4.3.8. s1_axi4 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR4 4.3.9. s2_axi4 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR4 4.3.10. s3_axi4 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR4 4.3.11. s0_axi4lite_clock for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR4 4.3.12. s0_axi4lite_reset_n for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR4 4.3.13. s0_axi4lite for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR4 4.3.14. s1_axi4lite_clock for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR4 4.3.15. s1_axi4lite_reset_n for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR4 4.3.16. s1_axi4lite for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR4 4.3.17. mem_0 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR4 4.3.18. mem_ck_0 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR4 4.3.19. mem_1 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR4 4.3.20. mem_ck_1 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR4 4.3.21. mem_2 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR4 4.3.22. mem_ck_2 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR4 4.3.23. mem_3 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR4 4.3.24. mem_ck_3 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR4 4.3.25. mem_reset_n for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR4 4.3.26. oct_0 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR4 4.3.27. oct_1 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR4 4.3.28. oct_2 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR4 4.3.29. oct_3 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR4 4.3.30. ref_clk for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR4
4.4. IP Interfaces for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR5 x
4.4.1. s0_axi4_clock_in for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.4.2. core_init_n for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.4.3. s0_axi4_ctrl_ready for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.4.4. s0_axi4_clock_out for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.4.5. s1_axi4_ctrl_ready for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.4.6. s1_axi4_clock_out for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.4.7. s0_axi4 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.4.8. s1_axi4 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.4.9. s2_axi4 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.4.10. s3_axi4 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.4.11. s0_axi4lite_clock for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.4.12. s0_axi4lite_reset_n for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.4.13. s0_axi4lite for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.4.14. s1_axi4lite_clock for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.4.15. s1_axi4lite_reset_n for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.4.16. s1_axi4lite for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.4.17. mem_0 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.4.18. mem_ck_0 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.4.19. mem_1 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.4.20. mem_ck_1 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.4.21. mem_2 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.4.22. mem_ck_2 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.4.23. mem_3 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.4.24. mem_ck_3 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.4.25. mem_reset_n for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.4.26. oct_0 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.4.27. oct_1 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.4.28. oct_2 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.4.29. oct_3 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.4.30. ref_clk for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR5
5. Agilex™ 5 FPGA EMIF IP – Simulating Memory IP x
5.1. Simulation Walkthrough
5.1. Simulation Walkthrough x
5.1.1. Calibration 5.1.2. Simulation Scripts 5.1.3. Functional Simulation with Verilog HDL 5.1.4. Simulating the Design Example
6. Agilex™ 5 FPGA EMIF IP - DDR4 Support x
6.1. External Memory Interfaces (EMIF) IP - DDR4 Component Parameter Descriptions 6.2. External Memory Interfaces (EMIF) IP - DDR4 DIMM Parameter Descriptions 6.3. Agilex™ 5 FPGA EMIF IP Pin and Resource Planning 6.4. Agilex™ 5 EMIF Pin Swapping Guidelines
6.3. Agilex™ 5 FPGA EMIF IP Pin and Resource Planning x
6.3.1. Agilex™ 5 FPGA EMIF IP Resources 6.3.2. Pin Guidelines for Agilex™ 5 FPGA EMIF IP 6.3.3. Pin Placements for Agilex™ 5 FPGA DDR4 EMIF IP
6.3.1. Agilex™ 5 FPGA EMIF IP Resources x
6.3.1.1. OCT 6.3.1.2. PLL
6.3.2. Pin Guidelines for Agilex™ 5 FPGA EMIF IP x
6.3.2.1. Agilex™ 5 FPGA EMIF IP Pin and Resource Planning
6.3.2.1. Agilex™ 5 FPGA EMIF IP Pin and Resource Planning x
6.3.2.1.1. Agilex™ 5 FPGA EMIF IP Interface Pins 6.3.2.1.2. Estimating Pin Requirements 6.3.2.1.3. Maximum Number of Interfaces
6.3.3. Pin Placements for Agilex™ 5 FPGA DDR4 EMIF IP x
6.3.3.1. Address and Command Pin Placement for DDR4 6.3.3.2. DDR4 Data Width Mapping 6.3.3.3. Clamshell Topology 6.3.3.4. General Guidelines 6.3.3.5. x4 DIMM Implementation 6.3.3.6. Specific Pin Connection Requirements 6.3.3.7. Command and Address Signals 6.3.3.8. Clock Signals 6.3.3.9. Data, Data Strobes, DM/DBI, and Optional ECC Signals
6.4. Agilex™ 5 EMIF Pin Swapping Guidelines x
6.4.1. DDR4 Byte Lane Swapping 6.4.2. DDR4 Address and Command and CLK Lane 6.4.3. DDR4 Interface x8 Data Lane 6.4.4. DDR4 Interface x4 Data Lane
7. Agilex™ 5 FPGA EMIF IP - DDR5 Support x
7.1. External Memory Interfaces (EMIF) IP - DDR5 Component Parameter Descriptions 7.2. External Memory Interfaces (EMIF) IP - DDR5 DIMM Parameter Descriptions 7.3. Agilex™ 5 FPGA EMIF IP Pin and Resource Planning
7.3. Agilex™ 5 FPGA EMIF IP Pin and Resource Planning x
7.3.1. Agilex™ 5 FPGA EMIF IP Interface Pins 7.3.2. Agilex™ 5 FPGA EMIF IP Resources 7.3.3. Pin Guidelines for Agilex™ 5 FPGA EMIF IP 7.3.4. Pin Placements for Agilex™ 5 FPGA DDR5 EMIF IP 7.3.5. Agilex™ 5 EMIF Pin Swapping Guidelines
7.3.1. Agilex™ 5 FPGA EMIF IP Interface Pins x
7.3.1.1. Estimating Pin Requirements 7.3.1.2. DIMM Options 7.3.1.3. Maximum Number of Interfaces
7.3.2. Agilex™ 5 FPGA EMIF IP Resources x
7.3.2.1. OCT 7.3.2.2. PLL
7.3.3. Pin Guidelines for Agilex™ 5 FPGA EMIF IP x
7.3.3.1. General Guidelines - DDR5 7.3.3.2. x4 DIMM Implementation 7.3.3.3. Specific Pin Connection Requirements 7.3.3.4. Command and Address Signals 7.3.3.5. Clock Signals 7.3.3.6. Data, Data Strobes, DM, and Optional ECC Signals
7.3.4. Pin Placements for Agilex™ 5 FPGA DDR5 EMIF IP x
7.3.4.1. Address and Command Pin Placement for DDR5 7.3.4.2. DDR5 Data Width Mapping
7.3.5. Agilex™ 5 EMIF Pin Swapping Guidelines x
7.3.5.1. DDR5 Byte Lane Swapping 7.3.5.2. DDR5 Address and Command and CLK Lane 7.3.5.3. DDR5 Interface x8 Data Lane 7.3.5.4. DDR5 Interface x4 Data Lane 7.3.5.5. Pin Swizzling
8. Agilex™ 5 FPGA EMIF IP - LPDDR4 Support x
8.1. External Memory Interfaces (EMIF) IP - LPDDR4 Parameter Descriptions 8.2. Agilex™ 5 FPGA EMIF IP Pin and Resource Planning
8.2. Agilex™ 5 FPGA EMIF IP Pin and Resource Planning x
8.2.1. Agilex™ 5 FPGA EMIF IP Interface Pins 8.2.2. Agilex™ 5 FPGA EMIF IP Resources 8.2.3. Pin Guidelines for Agilex™ 5 FPGA EMIF IP
8.2.1. Agilex™ 5 FPGA EMIF IP Interface Pins x
8.2.1.1. Estimating Pin Requirements 8.2.1.2. LPDDR4 Component Options 8.2.1.3. Maximum Number of Interfaces
8.2.2. Agilex™ 5 FPGA EMIF IP Resources x
8.2.2.1. OCT 8.2.2.2. PLL
8.2.3. Pin Guidelines for Agilex™ 5 FPGA EMIF IP x
8.2.3.1. General Guidelines 8.2.3.2. Specific Pin Connection Requirements 8.2.3.3. Command and Address Signals 8.2.3.4. Clock Signals 8.2.3.5. Address and Command Pin Placement for LPDDR4 8.2.3.6. LPDDR4 Data Width Mapping 8.2.3.7. Pin Swapping Guidelines
9. Agilex™ 5 FPGA EMIF IP - LPDDR5 Support x
9.1. External Memory Interfaces (EMIF) IP - LPDDR5 Parameter Descriptions 9.2. Agilex™ 5 FPGA EMIF IP Pin and Resource Planning
9.2. Agilex™ 5 FPGA EMIF IP Pin and Resource Planning x
9.2.1. Agilex™ 5 FPGA EMIF IP Interface Pins 9.2.2. Agilex™ 5 FPGA EMIF IP Resources 9.2.3. Pin Guidelines for Agilex™ 5 FPGA EMIF IP 9.2.4. Pin Placements for Agilex™ 5 FPGA LPDDR5 EMIF IP
9.2.1. Agilex™ 5 FPGA EMIF IP Interface Pins x
9.2.1.1. Estimating Pin Requirements 9.2.1.2. LPDDR5 Component Options 9.2.1.3. Maximum Number of Interfaces
9.2.2. Agilex™ 5 FPGA EMIF IP Resources x
9.2.2.1. OCT 9.2.2.2. PLL
9.2.3. Pin Guidelines for Agilex™ 5 FPGA EMIF IP x
9.2.3.1. General Guidelines - LPDDR5 9.2.3.2. Specific Pin Connection Requirements 9.2.3.3. Command and Address Signals 9.2.3.4. Clock Signals
9.2.4. Pin Placements for Agilex™ 5 FPGA LPDDR5 EMIF IP x
9.2.4.1. Address and Command Pin Placement for LPDDR5 9.2.4.2. LPDDR5 Data Width Mapping 9.2.4.3. LPDDR5 Byte Lane Swapping
10. Agilex™ 5 FPGA EMIF IP – Timing Closure x
10.1. Timing Closure 10.2. Optimizing Timing
10.1. Timing Closure x
10.1.1. Timing Analysis
10.1.1. Timing Analysis x
10.1.1.1. PHY or Core
11. Agilex™ 5 FPGA EMIF IP – Controller Optimization x
11.1. Optimizing Efficiency for Secondary Controller 11.2. Interface Standard 11.3. Bank Management Efficiency 11.4. Data Transfer 11.5. Improving Controller Efficiency
11.5. Improving Controller Efficiency x
11.5.1. Frequency of Operation 11.5.2. Series of Reads or Writes 11.5.3. AXI to Memory Mapping
12. Agilex™ 5 FPGA EMIF IP – Debugging x
12.1. Interface Configuration Performance Issues 12.2. Functional Issue Evaluation 12.3. Timing Issue Characteristics 12.4. Verifying Memory IP Using the Signal Tap Logic Analyzer 12.5. Debugging with the External Memory Interface Debug Toolkit 12.6. Generating Traffic with the Test Engine IP 12.7. Guidelines for Developing HDL for Traffic Generator 12.8. Guidelines for Traffic Generator Status Check 12.9. Hardware Debugging Guidelines 12.10. Categorizing Hardware Issues
12.1. Interface Configuration Performance Issues x
12.1.1. Interface Configuration Bottleneck and Efficiency Issues
12.2. Functional Issue Evaluation x
12.2.1. Altera IP Memory Model 12.2.2. Vendor Memory Model 12.2.3. Transcript Window Messages
12.3. Timing Issue Characteristics x
12.3.1. Evaluating FPGA Timing Issues 12.3.2. Evaluating External Memory Interface Timing Issues
12.5. Debugging with the External Memory Interface Debug Toolkit x
12.5.1. Prerequisites for Using the EMIF Debug Toolkit 12.5.2. Configuring a Design to Use the Debug Toolkit 12.5.3. Launching the EMIF Debug Toolkit 12.5.4. Using the EMIF Debug Toolkit
12.5.2. Configuring a Design to Use the Debug Toolkit x
12.5.2.1. Generating a Design Example with the Debug Toolkit
12.5.4. Using the EMIF Debug Toolkit x
12.5.4.1. Running Re-Calibration 12.5.4.2. Running the Test Engine
12.8. Guidelines for Traffic Generator Status Check x
12.8.1. Status Check Using the Signal Tap Logic Analyzer 12.8.2. Exporting the Status Interface to the Top-Level Design
12.9. Hardware Debugging Guidelines x
12.9.1. Create a Simplified Design that Demonstrates the Same Issue 12.9.2. Measure Power Distribution Network 12.9.3. Measure Signal Integrity and Setup and Hold Margin 12.9.4. Vary Voltage 12.9.5. Operate at a Lower Speed 12.9.6. Determine Whether the Issue Exists in Previous Versions of Software 12.9.7. Determine Whether the Issue Exists in the Current Version of Software 12.9.8. Try A Different PCB 12.9.9. Try Other Configurations 12.9.10. Debugging Checklist
12.10. Categorizing Hardware Issues x
12.10.1. Signal Integrity Issues 12.10.2. Hardware and Calibration Issues
12.10.1. Signal Integrity Issues x
12.10.1.1. Characteristics of Signal Integrity Issues 12.10.1.2. Evaluating Signal Integrity Issues 12.10.1.3. Skew 12.10.1.4. Crosstalk 12.10.1.5. Power System 12.10.1.6. Clock Signals 12.10.1.7. Address and Command Signals 12.10.1.8. Read Data Valid Window and Eye Diagram 12.10.1.9. Write Data Valid Window and Eye Diagram
12.10.2. Hardware and Calibration Issues x
12.10.2.1. Verifying High-Level Configuration 12.10.2.2. Verifying Memory Timing Parameters 12.10.2.3. Verifying the Correct Memory Component or DIMM Installed 12.10.2.4. Debugging Intermittent Issues
13. Agilex™ 5 FPGA EMIF IP - Mailbox Support x
13.1. Agilex™ 5 Mailbox Structure and Register Definitions 13.2. Accessing Read-Only Registers 13.3. Sending a Mailbox Command 13.4. IOSSM Mailbox Access Script
13.1. Agilex™ 5 Mailbox Structure and Register Definitions x
13.1.1. Mailbox Supported Commands Read-Only Registers Mailbox Supported Commands 13.1.2. Mailbox Command Definitions 13.1.3. ECC Syndrome Codes 13.1.4. ECC Error Handling
13.2. Accessing Read-Only Registers x
13.2.1. Example 1: Reading IP_TYPE and IP_INSTANCE_ID of All the Interfaces in the IO96B Through Read-Only Registers 13.2.2. Example 2: Reading the Memory Clock Frequency for an Interface
13.3. Sending a Mailbox Command x
13.3.1. Example 3: Sending Recalibration Request and Reading Calibration Status Using the Mailbox
13.3.1. Example 3: Sending Recalibration Request and Reading Calibration Status Using the Mailbox x
13.3.1.1. Example 4: Sending ECC_INJECT_ERROR Using the Mailbox and Reading ECC Error Status, ECC Error Buffer Registers
13.4. IOSSM Mailbox Access Script x
13.4.1. Mailbox Script Overview 13.4.2. Running the Mailbox Script
13.4.1. Mailbox Script Overview x
13.4.1.1. mb_iossm_command.tcl 13.4.1.2. mb_user_input.tcl
1. About the External Memory Interfaces Agilex™ 5 FPGA IP
2. Agilex™ 5 FPGA EMIF IP – Introduction
3. Agilex™ 5 FPGA EMIF IP – Product Architecture
4. Agilex™ 5 FPGA EMIF IP – End-User Signals
5. Agilex™ 5 FPGA EMIF IP – Simulating Memory IP
6. Agilex™ 5 FPGA EMIF IP - DDR4 Support
7. Agilex™ 5 FPGA EMIF IP - DDR5 Support
8. Agilex™ 5 FPGA EMIF IP - LPDDR4 Support
9. Agilex™ 5 FPGA EMIF IP - LPDDR5 Support
10. Agilex™ 5 FPGA EMIF IP – Timing Closure
11. Agilex™ 5 FPGA EMIF IP – Controller Optimization
12. Agilex™ 5 FPGA EMIF IP – Debugging
13. Agilex™ 5 FPGA EMIF IP - Mailbox Support
14. Document Revision History for External Memory Interfaces (EMIF) IP User Guide

13.1.1. Mailbox Supported Commands

Read-Only Registers

The following read-only registers provide direct access to retrieve information. Note that these registers are not write-protected; you should not attempt to write to any of these registers. Additionally, you should avoid reading from registers that are not used in the target design, as doing so might result in unpredictable or invalid data being returned.

Table 235.  Read-Only Registers
Register Name Byte Offset (Hexadecimal) Description
MAILBOX_HEADER 0x000

[Output] Mailbox Header

This register specifies information about the mailbox protocol.

[Fields]

[2:0] MB_SPEC_VER: This field specifies the version of mailbox specification being used by the IOSSM firmware.

Current version number is 1.
MEM_INTF_INFO_0 0x200

[Output] Memory Interface Information

This register specifies the memory interface IP type and instance ID for the interface 0/1 in the IO96B. It will only return the primary interface of each channel.

[Fields]

[31:29] IP_TYPE: Indicates the type of IP:

  • 0x0 – Not used.
  • 0x1 – Primary MC of Primary IO96B.
  • 0x2 – Secondary MC of Primary IO96B.
  • 0x3 – Primary MC of Secondary IO96B.
  • 0x4 – Secondary MC of Secondary IO96B.
[28:24] INSTANCE_ID: IP identifier.
MEM_INTF_INFO_1 0x280
MEM_TECHNOLOGY_INTF0 0x210

[Output] Memory Technology

This register provides the memory technology type for the memory interface 0/1.

[Fields]

[2:0] TECH: Reports the memory technology type:
  • 0x0 = DDR4
  • 0x1 = DDR5
  • 0x2 = DDR5_RDIMM
  • 0x3 = LPDDR4
  • 0x4 = LPDDR5
MEM_TECHNOLOGY_INTF1 0x290
MEMCLK_FREQ_INTF0 0x220

[Output] Memory Clock Frequency - This register reports the memory clock frequency in kilohertz (KHz) for the memory interface 0/1. For protocols with multiple FSPs, it reports the current memory clock frequency in kilohertz (KHz).

[Fields]

[31:0] FREQ_KHZ_FSP_CUR: Current memory clock frequency in KHz.
MEMCLK_FREQ_INTF1 0x2A0
MEMCLK_FREQ_FSP0_INTF0 0x224

[Output] Memory Clock Frequency - Frequency Set Point 0

This register reports the memory clock frequency in kilohertz (KHz) for Frequency Set Point 0 of the memory interface 0/1. Only valid for LPDDR5 protocol.

[Fields]

[31:0] FREQ_KHZ_FSP0: Memory clock frequency in KHz for Frequency Set Point 0.
MEMCLK_FREQ_FSP0_INTF1 0x2A4
MEMCLK_FREQ_FSP1_INTF0 0x228

[Output] Memory Clock Frequency - Frequency Set Point 1

This register reports the memory clock frequency in kilohertz (KHz) for Frequency Set Point 1 of the memory interface 0/1. Only valid for LPDDR5 protocol.

[Fields]

[31:0] FREQ_KHZ_FSP1: Memory clock frequency in KHz for Frequency Set Point 1.
MEMCLK_FREQ_FSP1_INTF1 0x2A8
MEMCLK_FREQ_FSP2_INTF0 0X22C

MEMCLK_FREQ_INTF0_FSP2

[Output] Memory Clock Frequency - Frequency Set Point 2

This register reports the memory clock frequency in kilohertz (KHz) for Frequency Set Point 2 of the memory interface 0/1. Only valid for LPDDR5 protocol.

[Fields]

[31:0] FREQ_KHZ_FSP2: Memory clock frequency in KHz for Frequency Set Point 2.
MEMCLK_FREQ_FSP2_INTF1 0x2AC
MEM_WIDTH_INFO_INTF0 0x230

[Output] Memory Width Information

This register provides the memory width information for the memory interface 0/1.

[Fields]

[23:16] C_WIDTH: Channel width.

[15:8] CS_WIDTH: Chip select width.

[7:0] DQ_WIDTH: Data width
MEM_WIDTH_INFO_INTF1 0x2B0
MEM_TOTAL_CAPACITY_INTF0 0x234

Output] Total Memory Capacity

This register reports the total memory capacity per channel in gigabits (Gb) for the memory interface 0/1.

[Fields]

[7:0] CAPACITY_GBITS: Total memory device capacity per channel in Gb. Total memory capacity is calculated as:

CAPACITY = (DQ_WIDTH / DEVICE_WIDTH) * NUM_RANKS * C_WIDTH * DEVICE_DENSITY
MEM_TOTAL_CAPACITY_INTF1 0x2B4
ECC_ENABLE_INTF0 0x240

[Output] ECC Enable Status

This register provides detailed information regarding the ECC enable status and type for the memory interface 0/1.

[Fields]

[18:18] RD_LINK_ECC_ENABLED: Indicates the Read Link-ECC enable status.

  • 1'b1 – Read Link-ECC is enabled.
  • 1'b0 – Read Link-ECC is disabled.

[17:17] WR_LINK_ECC_ENABLED: Indicates the Write Link-ECC enable status.

  • 1'b1 – Write Link-ECC is enabled.
  • 1'b0 – Write Link-ECC is disabled.

[16:16] LINK_ECC_SUPPORTED: Indicates if Link-ECC is supported by the interface.

  • 1'b1 – Link-ECC is supported.
  • 1'b0 – Link-ECC is not supported.

[8:8] ECC_TYPE: Specifies the ECC operational mode.

  • 1'b0 – Out-of-Band ECC.
  • 1'b1 – In-line ECC.
[1:0] ECC_ENABLE_TYPE: Reports the current ECC error reporting and correcting status.
  • 1'b00 – ECC is disabled. Data will be written and returned without ECC verification.
  • 1'b01 – ECC is enabled without error detection or correction.
  • 1'b10 – ECC is enabled with error detection; errors are reported but not corrected.
  • 1'b11 – ECC is enabled with error detection and correction; single-bit errors are automatically corrected.
ECC_ENABLE_INTF1 0x2C0
ECC_SCRUB_STATUS_INTF0 0x244

[Output] ECC Scrub Status

This register indicates the ECC scrub operation status for the memory interface 0/1.

[Fields]

[1:1] ECC_SCRUB_IN_PROGRESS: Reports whether an ECC scrub operation is currently in progress.
  • 1'b0 – Not actively performing a scrubbing operation.
  • 1'b1 – The Controller is in the process of performing a scrubbing operation.
[0:0] ECC_SCRUB_STATUS: The ECC scrub operation initiated using ECC_SCRUB_MODE_0/1_START mailbox command has completed.
  • 1'b0 – Scrubbing operation has not completed.
  • 1'b1 – Scrubbing operation has completed.
ECC_SCRUB_STATUS_INTF1 0x2C4
LP_MODE_INTF0 0x250

[Output] Low Power Mode Status

This register provides the current low power state and its validity for the memory interface 0/1.

[Fields]

[5:0] LP_STATE: Current Interface Low Power State.
  • 1'b000000 – Idle.
  • 1'b000001 – Active Power Down.
  • 1'b000010 – Active Power Down with Memory Clock Gating.
  • 1'b000011 – Pre-Charge Power Down.
  • 1'b000100 – Pre-Charge Power Down with Memory Clock Gating.
  • 1'b000101 – Self-Refresh Short.
  • 1'b000110 – Self-Refresh Short with Memory Clock Gating.
  • 1'b001000 – Self-Refresh Long.
  • 1'b001001 – Self-Refresh Long with Memory Clock Gating.
  • 1'b001010 – Self-Refresh Long with Memory Clock and Controller Clock Gating.
  • 1'b001011 – Self-Refresh Power Down Short.
  • 1'b001100 – Self-Refresh Power Down Short with Memory Clock Gating.
  • 1'b001101 – Self-Refresh Power Down.
  • 1'b001110 – Self-Refresh Power Down Long with Memory Clock Gating.
  • 1'b001111 – Self-Refresh Power Down Long with Memory and Controller Clock Gating.
[6:6] LP_STATE_VALID: Indicates whether the data for the low power state is valid.
  • 1'b1 – Valid. The low power state information is reliable.
  • 1'b0 – Invalid. The interface is currently transitioning into or out of a low power state.
LP_MODE_INTF1 0x2D0
MEM_INIT_STATUS_INTF0 0x260

[Output] BIST Memory Initialization Status

This register holds the status of the BIST memory initialization operation for the memory interface specified by the instance ID. The value of this register is only valid if the mailbox command BIST_MEM_INIT_START was issued previously.

[Fields]

[0:0] MEM_INIT_STATUS: Indicates the status of the BIST memory content initialization operation.
  • 1'b0 – Memory content initialization operation still in progress if previously initiated.
  • 1'b1 – Memory content initialization operation has been completed.
MEM_INIT_STATUS_INTF1 0x2E0
BIST_STATUS_INTF0 0x264

[Output] BIST Results Status

This register contains BIST results for the previously initiated BIST operation for memory interface 0/1

[Fields]

[31:16] BIST_FAIL_RESULT_OFFSET: Holds the offset pointer of the BIST failure results. The data at the pointer location will be as below:
  • OFFSET [0] to OFFSET [8]: [287:0]BIST_EXP_DATA - Holds the expected read data for BIST data check failure.
  • OFFSET [9] to OFFSET [10]: [37:0]BIST_FAIL_ADDR - Holds the actual failing address for BIST data check failure.
  • OFFSET [11] to OFFSET [20]: [287:0] BIST_FAIL_DATA - Holds the actual failing data for BIST data check failure. [15:8] BIST_FAIL_RESULT_SIZE: Holds the size of the BIST failure results. The value of this will be 640 bits.
[1:1] BIST_RESULT: Holds the result of the BIST operation. For this BIST mode, the test will end at the first failure, or completely check the specified data range if no failures were found. This value is valid when BIST_STATUS indicates that the BIST operation has completed.
  • 1'b0 = Data check failed.
  • 1'b1 = Data check passed.
[0:0] BIST_STATUS: Indicates the status of the BIST operation.
  • 1'b0 – BIST operation still in progress if previously initiated.
  • 1'b1 – BIST operation has been completed.
BIST_STATUS_INTF1 0x2E4
ECC_ERR_STATUS 0x300

[Output] ECC Error Status

This register contains the status of the ECC error buffer.

[Fields]

[31:16] ECC_ERR_OVERFLOW: This field indicates that buffer overflow has occurred due to a new ECC interrupt occurring after the ECC error buffer is at full capacity of 16 entries. Each new interrupt type that cannot be enqueued into the buffer are logically-OR’d to the existing contents of the overflow status field. The ECC interrupt types indicated by the different positional bits in the overflow field are as below:
  • [0] – Single-bit error.
  • [1] – Multiple single-bit errors.
  • [2] – Double-bit error.
  • [3] – Multiple double-bit errors.
  • [8] – Single-bit error during ECC scrubbing.
  • [9] – Write link ECC single-bit error (LPDDR5 only).
  • [10] – Write link ECC double-bit error (LPDDR5 only).
  • [11] – Read link ECC single-bit error (LPDDR5 only).
  • [12] – Read link ECC double-bit error (LPDDR5 only).
  • [13] – RMW read link ECC double-bit error (LPDDR5 only).
[15:0] ECC_ERR_COUNTER: This field indicates the number of entries in ECC error buffer. The buffer has a maximum capacity of 16 entries after which overflow occurs. The mailbox command ECC_CLEAR_ERR_BUFFER clears the ECC error buffer and resets the ECC_ERR_COUNTER to 0.
ECC_ERR_DATA_START 0x310

[Output] ECC Error Data Start

This register is the start of the ECC error data buffer. The buffer has a maximum capacity of 16 ECC errors. Each ECC error data entry has a size of 64 bits arranged in two 32-bit registers (Register 1 and Register 2 ). The mailbox command ECC_CLEAR_ERR_BUFFER clears the ECC error buffer and resets the ECC_ERR_COUNTER to 0.

[Fields]

R1[24:22] IP_TYPE: This field specifies the IP type of the interface that produced the ECC interrupt. IP_TYPE of 0 indicates that the buffer entry is not populated with valid data.

R1[21:17] INSTANCE_ID: This field specifies the instance ID of the interface that produced the ECC interrupt.

R1[16:10] ECC_ERR_SOURCE_ID: This field specifies the source ID associated with the ECC event. For AXI ports, the source ID is comprised of the Port ID (upper bit/s) and the Requestor ID, where the Requestor ID is the axi0_AWID for write commands or the axi0_ARID for read commands.

R1[9:6] ECC_ERR_TYPE: This field specifies the ECC interrupt type of the ECC event.
  • 1'b0000 – Single-bit error.
  • 1'b0001 – Multiple single-bit errors.
  • 1'b0010 – Double-bit error.
  • 1'b0011 – Multiple double-bit errors.
  • 1'b1000 – Single-bit error during ECC scrubbing.
  • 1'b1001 – Write link ECC single-bit error (LPDDR5 only).
  • 1'b1010 – Write link ECC double-bit error (LPDDR5 only).
  • 1'b1011 – Read link ECC single-bit error (LPDDR5 only)
  • 1'b1100 – Read link ECC double-bit error (LPDDR5 only).
  • 1'b1101 – Read link ECC double-bit error, caused by read-modify-write operation (LPDDR5 only).

R1[5:0] ECC_ERR_ADDR_UPPER: This field specifies the upper 6 bits of the address of the read data that caused the ECC event. The Controller will pad this parameter with zeros for any address bits not used by the controller.

R2[31:0] ECC_ERR_ADDR_LOWER: This field specifies the lower 32 bits of the address of the read data that caused the ECC event. The Controller will pad this parameter with zeros for any address bits not used by the controller.

Note: Refer to ECC Error Handling for details on ECC Error Buffer Byte Offset.
STATUS 0x400

[Output] Status Register

“At a Glance” status register. This field is automatically updated by the Calibration IOSSM and no explicit operation is required to trigger an update.

  • 1'b001 – Calibration was successful.
  • 1'b010 – Calibration failed.
  • 1'b100 – Calibration ongoing.
  • 1'b000 – Interface unused.
STATUS_CAL_INTF0 0x404

[Output] Memory Calibration Status

This register provides the calibration status for memory interface 0/1.

[Fields]

[2:0] STATUS: Calibration Status of memory interface
  • 1'b001 – Calibration was successful.
  • 1'b010 – Calibration failed.
  • 1'b100 – Calibration ongoing.
  • 1'b000 – Interface unused.
STATUS_CAL_INTF1 0x408

Mailbox Supported Commands

The following registers require handshaking procedures with the mailbox for successful retrieval of information. Refer to the instructions described in Sending a Mailbox Command for more information on handshaking procedures.

Table 236.  Supported Commands
CMD_TYPE Enum CMD_OPCODE Enum Value
CMD_TRIG_CONTROLLER_OP (value=0x4) ECC_ENABLE_SET 0x0101
ECC_INTERRUPT_MASK 0x0105
ECC_WRITEBACK_ENABLE 0x0106
ECC_INJECT_ERROR 0x0109
ECC_CLEAR_ERR_BUFFER 0x0110
ECC_SCRUB_MODE_0_START 0x0202
ECC_SCRUB_MODE_1_START 0x0203
BIST_STANDARD_MODE_START 0x0301
BIST_MEM_INIT_START 0x0303
BIST_SET_DATA_PATTERN_UPPER 0x0305
BIST_SET_DATA_PATTERN_LOWER 0x0306
CHANGE_FSP_LP5 0x0c01
LP_MODE_ENTER 0x0d01
LP_MODE_EXIT 0x0d02
LP_MODE_AUTO 0x0d04

CMD_TRIG_MEM_CAL_OP ​ (value=0x5)

 TRIG_MEM_CAL 0x000a
Level Two Title