External Memory Interfaces (EMIF) IP User Guide: Agilex™ 5 FPGAs and SoCs

ID 817467
Date 3/31/2025
Public
Document Table of Contents

4.4.21. mem_2 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR5

Interface to the memory (channel 2), including all CA pins, DQ pins, and DQS pins.

Table 112.  Interface: mem_2Interface type: conduit
Port Name Direction Description
mem_2_cs Output Chip Select channel 2.
mem_2_ca Output Command/Address Bus channel 2.
mem_2_dq Bidir Data (read/write) channel 2.
mem_2_rdqs_t Bidir Read Data Strobe (true) channel 2.
mem_2_rdqs_c Bidir Read Data Strobe (complement) channel 2.
mem_2_dmi Bidir Data Mask/Data Inversion channel 2.
mem_2_wck_t Output Write Clock (true) channel 2.
mem_2_wck_c Output Write Clock (complement) channel 2.