External Memory Interfaces (EMIF) IP User Guide: Agilex™ 5 FPGAs and SoCs

ID 817467
Date 3/31/2025
Public
Document Table of Contents

4.4.26. oct_0 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR5

On-Chip Termination (OCT) interface, representing RZQ pin (channel 0).

Table 117.  Interface: oct_0Interface type: conduit
Port Name Direction Description
oct_rzqin_0 Input Calibrated On-Chip Termination (OCT) input pin channel 0.