External Memory Interfaces (EMIF) IP User Guide: Agilex™ 5 FPGAs and SoCs

ID 817467
Date 3/31/2025
Public
Document Table of Contents

4.4.30. ref_clk for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR5

Reference clock used by the EMIF PLL.

Table 121.  Interface: ref_clkInterface type: clock
Port Name Direction Description
ref_clk Input PLL reference clock input.