External Memory Interfaces (EMIF) IP User Guide: Agilex™ 5 FPGAs and SoCs

ID 817467
Date 3/31/2025
Public
Document Table of Contents

4.2.14. mem_ck_1 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - DDR5 Component

Clock pin to the memory (channel 1).

Table 55.  Interface: mem_ck_1Interface type: conduit
Port Name Direction Description
mem_1_ck_t Output CK Clock (true) channel 1.
mem_1_ck_c Output CK Clock (complement) channel 1.