External Memory Interfaces (EMIF) IP User Guide: Agilex™ 5 FPGAs and SoCs

ID 817467
Date 3/31/2025
Public
Document Table of Contents

4.2.13. mem_1 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - DDR5 Component

Interface to the memory (channel 1), including all CA pins, DQ pins, and DQS pins.

Table 54.  Interface: mem_1Interface type: conduit
Port Name Direction Description
mem_1_cs_n Output Chip Select channel 1.
mem_1_ca Output Command/Address Bus channel 1.
mem_1_dq Bidir Data (read/write) channel 1.
mem_1_dqs_t Bidir Data Strobe (true) channel 1.
mem_1_dqs_c Bidir Data Strobe (complement) channel 1.
mem_1_alert_n Input Indicates Write CRC Error channel 1.