External Memory Interfaces (EMIF) IP User Guide: Agilex™ 5 FPGAs and SoCs

ID 817467
Date 3/31/2025
Public
Document Table of Contents

4.4.12. s0_axi4lite_reset_n for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR5

Reset for sideband interface (primary I/O bank).

Table 103.  Interface: s0_axi4lite_reset_nInterface type: reset
Port Name Direction Description
s0_axi4lite_reset_n Input Axi-Lite reset_n, to primary IOSSM.