Visible to Intel only — GUID: qsx1683566196545
Ixiasoft
- 4.1.2. s0_axi4_clock_out for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - DDR4 Component
- 4.2.2. s0_axi4_clock_out for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - DDR5 Component
Visible to Intel only — GUID: qsx1683566196545
Ixiasoft
3.5. Agilex™ 5 EMIF IP for Hard Processor Subsystem (HPS)
To enable connectivity between the HPS and the Agilex™ 5 EMIF IP, you must create and configure an instance of the EMIF for HPS IP, and connect it to the Agilex™ 5 FPGA hard processor subsystem instance in your system.
HPS EMIF Mapping (Both bridges are used)
When using both the F2H bridge and the F2SDRAM bridge, no I/O sharing is allowed. That is, the HPS can access DDR and fabric can access DDR via the F2H and/or F2SDRAM bridge, but no GPIO, etc is allowed.
Protocol | Banks | Data Width | BL7 | BL6 | BL5 | BL4 | BL3 | BL2 | BL1 | BL0 |
---|---|---|---|---|---|---|---|---|---|---|
DDR4 | 1 | 1x16 | X | X | X | DQ[1] | AC2 | AC1 | AC0 | DQ[0] |
1 | 1x16+ECC | X | X | DQ[ECC] | DQ[1] | AC2 | AC1 | AC0 | DQ[0] | |
1 or 2 | 1x32 | X | DQ[3] | DQ[2] | DQ[1] | AC2 | AC1 | AC0 | DQ[0] | |
1 or 2 | 1x32+ECC | DQ[ECC] | DQ[3] | DQ[2] | DQ[1] | AC2 | AC1 | AC0 | DQ[0] | |
1 | 1x16 | DQ[0] | AC0 | AC2 | AC1 | DQ[1] | X | X | X | |
1 | 1x16+ECC | DQ[0] | AC0 | AC2 | AC1 | DQ[1] | DQ[ECC] | X | X | |
1 or 2 | 1x32 | DQ[0] | AC0 | AC2 | AC1 | DQ[1] | DQ[2] | DQ[3] | X | |
1 or 2 | 1x32+ECC | DQ[0] | AC0 | AC2 | AC1 | DQ[1] | DQ[2] | DQ[3] | DQ[ECC] | |
N/A | 1x64 | Not supported | ||||||||
N/A | 1x64+ECC | Not supported | ||||||||
DDR5 | 1 | 1x16 | X | X | X | X | AC1 | AC0 | DQ[0] | DQ[1] |
1 | 1x16+ECC | X | X | X | DQ[ECC] | AC1 | AC0 | DQ[0] | DQ[1] | |
1 or 2 | 1x32 | X | X | DQ[3] | DQ[2] | AC1 | AC0 | DQ[0] | DQ[1] | |
1 or 2 | 1x32+ECC | X | DQ[ECC] | DQ[3] | DQ[2] | AC1 | AC0 | DQ[0] | DQ[1] | |
1 | 1x16 | DQ[1] | DQ[0] | AC1 | AC0 | X | X | X | X | |
1 | 1x16+ECC | DQ[1] | DQ[0] | AC1 | AC0 | DQ[ECC] | X | X | X | |
1 or 2 | 1x32 | DQ[1] | DQ[0] | AC1 | AC0 | DQ[2] | DQ[3] | X | X | |
1 or 2 | 1x32+ECC | DQ[1] | DQ[0] | AC1 | AC0 | DQ[2] | DQ[3] | DQ[ECC] | X | |
1 | 2x16 | DQ[1] | DQ[0] | AC1 | AC0 | AC1 | AC0 | DQ[0] | DQ[1] | |
LPDDR4 / LPDDR5 | 1 | 1x16 | X | X | X | X | AC1 | AC0 | DQ[1] | DQ[0] |
1 or 2 | 1x32 | DQ[3] | DQ[2] | X | X | AC1 | AC0 | DQ[1] | DQ[0] | |
1 | 2x16 | DQ[1] | DQ[0] | AC1 | AC0 | AC1 | AC0 | DQ[1] | DQ[0] | |
2 | 4x16 | DQ[1] | DQ[0] | AC1 | AC0 | AC1 | AC0 | DQ[1] | DQ[0] | |
|
HPS EMIF Mapping (Using only the F2SDRAM bridge)
The following table shows the I/O sharing that is allowed when using the F2SDRAM bridge and not using the F2H bridge. The HPS can access DDR and fabric can access DDR via the F2SDRAM bridge only.
Protocol | Banks | Data Width | BL7 | BL6 | BL5 | BL4 | BL3 | BL2 | BL1 | BL0 |
---|---|---|---|---|---|---|---|---|---|---|
DDR4 | 1 | 1x16 | GM | GM | RZ | DQ[1] | AC2 | AC1 | AC0 | DQ[0] |
1 | 1x16+ECC | GO | GO | DQ[ECC] | DQ[1] | AC2 | AC1 | AC0 | DQ[0] | |
1 or 2 | 1x32 | GO | DQ[3] | DQ[2] | DQ[1] | AC2 | AC1 | AC0 | DQ[0] | |
1 or 2 | 1x32+ECC | DQ[ECC] | DQ[3] | DQ[2] | DQ[1] | AC2 | AC1 | AC0 | DQ[0] | |
1 | 1x16 | DQ[0] | AC0 | AC2 | AC1 | DQ[1] | X | X | X | |
1 | 1x16+ECC | DQ[0] | AC0 | AC2 | AC1 | DQ[1] | DQ[ECC] | X | X | |
1 or 2 | 1x32 | DQ[0] | AC0 | AC2 | AC1 | DQ[1] | DQ[2] | DQ[3] | X | |
1 or 2 | 1x32+ECC | DQ[0] | AC0 | AC2 | AC1 | DQ[1] | DQ[2] | DQ[3] | DQ[ECC] | |
N/A | 1x64 | Not supported | ||||||||
N/A | 1x64+ECC | Not supported | ||||||||
DDR5 | 1 | 1x16 | GM | GM | RZ | GM | AC1 | AC0 | DQ[0] | DQ[1] |
1 | 1x16+ECC | GM | GM | RZ | DQ[ECC] | AC1 | AC0 | DQ[0] | DQ[1] | |
1 or 2 | 1x32 | GO | GO | DQ[3] | DQ[2] | AC1 | AC0 | DQ[0] | DQ[1] | |
1 or 2 | 1x32+ECC | GO | DQ[ECC] | DQ[3] | DQ[2] | AC1 | AC0 | DQ[0] | DQ[1] | |
1 | 1x16 | DQ[1] | DQ[0] | AC1 | AC0 | X | X | X | X | |
1 | 1x16+ECC | DQ[1] | DQ[0] | AC1 | AC0 | DQ[ECC] | X | X | X | |
1 or 2 | 1x32 | DQ[1] | DQ[0] | AC1 | AC0 | DQ[2] | DQ[3] | X | X | |
1 or 2 | 1x32+ECC | DQ[1] | DQ[0] | AC1 | AC0 | DQ[2] | DQ[3] | DQ[ECC] | X | |
1 | 2x16 | DQ[1] | DQ[0] | AC1 | AC0 | AC1 | AC0 | DQ[0] | DQ[1] | |
LPDDR4 / LPDDR5 | 1 | 1x16 | GM | GM | RZ | GM | AC1 | AC0 | DQ[1] | DQ[0] |
1 or 2 | 1x32 | DQ[3] | DQ[2] | RZ | GM | AC1 | AC0 | DQ[1] | DQ[0] | |
1 | 2x16 | DQ[1] | DQ[0] | AC1 | AC0 | AC1 | AC0 | DQ[1] | DQ[0] | |
2 | 4x16 | DQ[1] | DQ[0] | AC1 | AC0 | AC1 | AC0 | DQ[1] | DQ[0] | |
|
HPS EMIF Mapping (Using only the F2H bridge)
The following table shows the I/O sharing permitted when using the F2H bridge and not using the F2SDRAM bridge. The HPS can access DDR and fabric can access DDR via the F2H bridge only.
Protocol | Banks | Data Width | BL7 | BL6 | BL5 | BL4 | BL3 | BL2 | BL1 | BL0 |
---|---|---|---|---|---|---|---|---|---|---|
DDR4 | 1 | 1x16 | X | X | X | DQ[1] | AC2 | AC1 | AC0 | DQ[0] |
1 | 1x16+ECC | X | X | DQ[ECC] | DQ[1] | AC2 | AC1 | AC0 | DQ[0] | |
1 or 2 | 1x32 | X | DQ[3] | DQ[2] | DQ[1] | AC2 | AC1 | AC0 | DQ[0] | |
1 or 2 | 1x32+ECC | DQ[ECC] | DQ[3] | DQ[2] | DQ[1] | AC2 | AC1 | AC0 | DQ[0] | |
1 | 1x16 | DQ[0] | AC0 | AC2 | AC1 | DQ[1] | GL | GL | GL | |
1 | 1x16+ECC | DQ[0] | AC0 | AC2 | AC1 | DQ[1] | DQ[ECC] | GO | GO | |
1 or 2 | 1x32 | DQ[0] | AC0 | AC2 | AC1 | DQ[1] | DQ[2] | DQ[3] | GO | |
1 or 2 | 1x32+ECC | DQ[0] | AC0 | AC2 | AC1 | DQ[1] | DQ[2] | DQ[3] | DQ[ECC] | |
N/A | 1x64 | Not supported | ||||||||
N/A | 1x64+ECC | Not supported | ||||||||
DDR5 | 1 | 1x16 | X | X | X | X | AC1 | AC0 | DQ[0] | DQ[1] |
1 | 1x16+ECC | X | X | X | DQ[ECC] | AC1 | AC0 | DQ[0] | DQ[1] | |
1 or 2 | 1x32 | X | X | DQ[3] | DQ[2] | AC1 | AC0 | DQ[0] | DQ[1] | |
1 or 2 | 1x32+ECC | X | DQ[ECC] | DQ[3] | DQ[2] | AC1 | AC0 | DQ[0] | DQ[1] | |
1 | 1x16 | DQ[1] | DQ[0] | AC1 | AC0 | RZ | GM | GM | GM | |
1 | 1x16+ECC | DQ[1] | DQ[0] | AC1 | AC0 | DQ[ECC] | GL | GL | GL | |
1 or 2 | 1x32 | DQ[1] | DQ[0] | AC1 | AC0 | DQ[2] | DQ[3] | GO | GO | |
1 or 2 | 1x32+ECC | DQ[1] | DQ[0] | AC1 | AC0 | DQ[2] | DQ[3] | DQ[ECC] | GO | |
1 | 2x16 | DQ[1] | DQ[0] | AC1 | AC0 | AC1 | AC0 | DQ[0] | DQ[1] | |
LPDDR4 / LPDDR5 | 1 | 1x16 | X | X | X | X | AC1 | AC0 | DQ[1] | DQ[0] |
1 or 2 | 1x32 | DQ[3] | DQ[2] | X | X | AC1 | AC0 | DQ[1] | DQ[0] | |
1 | 2x16 | DQ[1] | DQ[0] | AC1 | AC0 | AC1 | AC0 | DQ[1] | DQ[0] | |
2 | 4x16 | DQ[1] | DQ[0] | AC1 | AC0 | AC1 | AC0 | DQ[1] | DQ[0] | |
|
HPS EMIF Mapping (No bridges are used)
The following table shows the I/O sharing permitted when using neither the F2H bridge nor the FS2DRAM bridge. The HPS can access DDR, but the fabric cannot.
Protocol | Banks | Data Width | BL7 | BL6 | BL5 | BL4 | BL3 | BL2 | BL1 | BL0 |
---|---|---|---|---|---|---|---|---|---|---|
DDR4 | 1 | 1x16 | GM | GM | RZ | DQ[1] | AC2 | AC1 | AC0 | DQ[0] |
1 | 1x16+ECC | GO | GO | DQ[ECC] | DQ[1] | AC2 | AC1 | AC0 | DQ[0] | |
1 or 2 | 1x32 | GO | DQ[3] | DQ[2] | DQ[1] | AC2 | AC1 | AC0 | DQ[0] | |
1 or 2 | 1x32+ECC | DQ[ECC] | DQ[3] | DQ[2] | DQ[1] | AC2 | AC1 | AC0 | DQ[0] | |
1 | 1x16 | DQ[0] | AC0 | AC2 | AC1 | DQ[1] | GL | GL | GL | |
1 | 1x16+ECC | DQ[0] | AC0 | AC2 | AC1 | DQ[1] | DQ[ECC] | GO | GO | |
1 or 2 | 1x32 | DQ[0] | AC0 | AC2 | AC1 | DQ[1] | DQ[2] | DQ[3] | GO | |
1 or 2 | 1x32+ECC | DQ[0] | AC0 | AC2 | AC1 | DQ[1] | DQ[2] | DQ[3] | DQ[ECC] | |
N/A | 1x64 | Not supported | ||||||||
N/A | 1x64+ECC | Not supported | ||||||||
DDR5 | 1 | 1x16 | GM | GM | RZ | GM | AC1 | AC0 | DQ[0] | DQ[1] |
1 | 1x16+ECC | GM | GM | RZ | DQ[ECC] | AC1 | AC0 | DQ[0] | DQ[1] | |
1 or 2 | 1x32 | GO | GO | DQ[3] | DQ[2] | AC1 | AC0 | DQ[0] | DQ[1] | |
1 or 2 | 1x32+ECC | GO | DQ[ECC] | DQ[3] | DQ[2] | AC1 | AC0 | DQ[0] | DQ[1] | |
1 | 1x16 | DQ[1] | DQ[0] | AC1 | AC0 | RZ | GM | GM | GM | |
1 | 1x16+ECC | DQ[1] | DQ[0] | AC1 | AC0 | DQ[ECC] | GL | GL | GL | |
1 or 2 | 1x32 | DQ[1] | DQ[0] | AC1 | AC0 | DQ[2] | DQ[3] | GO | GO | |
1 or 2 | 1x32+ECC | DQ[1] | DQ[0] | AC1 | AC0 | DQ[2] | DQ[3] | DQ[ECC] | GO | |
1 | 2x16 | DQ[1] | DQ[0] | AC1 | AC0 | AC1 | AC0 | DQ[0] | DQ[1] | |
LPDDR4 / LPDDR5 | 1 | 1x16 | GM | GM | RZ | GM | AC1 | AC0 | DQ[1] | DQ[0] |
1 or 2 | 1x32 | DQ[3] | DQ[2] | RZ | GM | AC1 | AC0 | DQ[1] | DQ[0] | |
1 | 2x16 | DQ[1] | DQ[0] | AC1 | AC0 | AC1 | AC0 | DQ[1] | DQ[0] | |
2 | 4x16 | DQ[1] | DQ[0] | AC1 | AC0 | AC1 | AC0 | DQ[1] | DQ[0] | |
|
I/O Sharing versus HPS EMIF DDR Protocol versus Bridge Allowed
The following table summarizes the information from the previous tables, showing which bridge can be used with which I/O sharing and DDR protocol combinations.
I/O Sharing | Protocol | Banks | Data Width | Bridge Allowed |
---|---|---|---|---|
MIPI or PHYLite | DDR4 | 1 | 1x16 | F2SDRAM |
DDR4 | 1 | 1x16 | F2SDRAM or F2H | |
1 | 1x16+ECC | F2SDRAM | ||
LPDDR4 / LPDDR5 | 1 | 1x16 | F2SDRAM | |
1 or 2 | 1x32 | F2SDRAM | ||
MIPI through RZQ sharing | DDR4 | 1 | 1x16 | F2H |
DDR5 | 1 | 1x16+ECC | F2H | |
MIPI through RZQ and refclk sharing | DDR4 | 1 | 1x16+ECC | F2SDRAM or F2H |
1 or 2 | 1x32 | F2SDRAM or F2H | ||
DDR5 | 1 or 2 | 1x32 | F2SDRAM or F2H | |
1 or 2 | 1x32+ECC | F2SDRAM or F2H | ||
LVDS | DDR4 | 1 | 1x16 | F2SDRAM or F2H |
DDR5 | 1 | 1x16 | F2SDRAM or F2H | |
1 | 1x16+ECC | F2SDRAM or F2H | ||
LPDDR4 / LPDDR5 | 1 | 1x16 | F2SDRAM | |
1 or 2 | 1x32 | F2SDRAM | ||
GPIO | DDR4 | 1 | 1x16 | F2SDRAM or F2H |
1 | 1x16+ECC | F2SDRAM or F2H | ||
1 or 2 | 1x32 | F2SDRAM or F2H | ||
DDR5 | 1 | 1x16 | F2SDRAM or F2H | |
1 | 1x16+ECC | F2SDRAM or F2H | ||
1 or 2 | 1x32 | F2SDRAM or F2H | ||
1 or 2 | 1x32+ECC | F2SDRAM or F2H | ||
LPDDR4 / LPDDR5 | 1 | 1x16 | F2SDRAM | |
1 or 2 | 1x32 | F2SDRAM |