External Memory Interfaces (EMIF) IP User Guide: Agilex™ 5 FPGAs and SoCs

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ID 817467
Date 3/31/2025
Public
Document Table of Contents
Document Table of Contents x
1. About the External Memory Interfaces Agilex™ 5 FPGA IP 2. Agilex™ 5 FPGA EMIF IP – Introduction 3. Agilex™ 5 FPGA EMIF IP – Product Architecture 4. Agilex™ 5 FPGA EMIF IP – End-User Signals 5. Agilex™ 5 FPGA EMIF IP – Simulating Memory IP 6. Agilex™ 5 FPGA EMIF IP - DDR4 Support 7. Agilex™ 5 FPGA EMIF IP - DDR5 Support 8. Agilex™ 5 FPGA EMIF IP - LPDDR4 Support 9. Agilex™ 5 FPGA EMIF IP - LPDDR5 Support 10. Agilex™ 5 FPGA EMIF IP – Timing Closure 11. Agilex™ 5 FPGA EMIF IP – Controller Optimization 12. Agilex™ 5 FPGA EMIF IP – Debugging 13. Agilex™ 5 FPGA EMIF IP - Mailbox Support 14. Document Revision History for External Memory Interfaces (EMIF) IP User Guide
1. About the External Memory Interfaces Agilex™ 5 FPGA IP x
1.1. Release Information
2. Agilex™ 5 FPGA EMIF IP – Introduction x
2.1. Agilex™ 5 EMIF IP Protocol and Feature Support 2.2. Agilex™ 5 EMIF IP Design Flow
2.2. Agilex™ 5 EMIF IP Design Flow x
2.2.1. Agilex™ 5 EMIF IP Design Checklist
3. Agilex™ 5 FPGA EMIF IP – Product Architecture x
3.1. Agilex™ 5 EMIF Architecture: Protocol and Maximum Interface Width Support 3.2. Agilex™ 5 EMIF Architecture: Introduction 3.3. Agilex™ 5 EMIF Sequencer 3.4. Agilex™ 5 EMIF Controller 3.5. Agilex™ 5 EMIF IP for Hard Processor Subsystem (HPS)
3.2. Agilex™ 5 EMIF Architecture: Introduction x
3.2.1. Agilex™ 5 EMIF Architecture: I/O Subsystem 3.2.2. Agilex™ 5 EMIF Architecture: I/O SSM 3.2.3. Agilex™ 5 EMIF Architecture: HSIO Bank 3.2.4. Agilex™ 5 EMIF Architecture: I/O Lane 3.2.5. Agilex™ 5 EMIF Architecture: Input DQS Clock Tree 3.2.6. Agilex™ 5 EMIF Architecture: PHY Clock Tree 3.2.7. Agilex™ 5 EMIF Architecture: PLL Reference Clock Networks 3.2.8. Agilex™ 5 EMIF Architecture: Clock Phase Alignment 3.2.9. User Clock in Different Core Access Modes
3.2.3. Agilex™ 5 EMIF Architecture: HSIO Bank x
3.2.3.1. Lockstep Configuration 3.2.3.2. Pin Placement 3.2.3.3. HSIO Sub-Bank Usage
3.4. Agilex™ 5 EMIF Controller x
3.4.1. Hard Memory Controller
3.4.1. Hard Memory Controller x
3.4.1.1. Hard Memory Controller Features
3.5. Agilex™ 5 EMIF IP for Hard Processor Subsystem (HPS) x
HPS EMIF Mapping (Both bridges are used) HPS EMIF Mapping (Using only the F2SDRAM bridge) HPS EMIF Mapping (Using only the F2H bridge) HPS EMIF Mapping (No bridges are used) I/O Sharing versus HPS EMIF DDR Protocol versus Bridge Allowed 3.5.1. Restrictions on I/O Bank Usage for EMIF IP with HPS 3.5.2. Using the Legacy EMIF Debug Toolkit with Agilex 5 HPS Interfaces
4. Agilex™ 5 FPGA EMIF IP – End-User Signals x
4.1. IP Interfaces for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - DDR4 Component 4.2. IP Interfaces for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - DDR5 Component 4.3. IP Interfaces for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR4 4.4. IP Interfaces for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR5
4.1. IP Interfaces for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - DDR4 Component x
4.1.1. s0_axi4_clock_in for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - DDR4 Component 4.1.2. s0_axi4_clock_out for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - DDR4 Component 4.1.3. s0_axi4_ctrl_ready for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - DDR4 Component 4.1.4. core_init_n for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - DDR4 Component 4.1.5. s0_axi4 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - DDR4 Component 4.1.6. s0_axi4lite_clock for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - DDR4 Component 4.1.7. s0_axi4lite_reset_n for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - DDR4 Component 4.1.8. s0_axi4lite for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - DDR4 Component 4.1.9. mem_0 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - DDR4 Component 4.1.10. mem_ck_0 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - DDR4 Component 4.1.11. mem_reset_n for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - DDR4 Component 4.1.12. oct_0 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - DDR4 Component 4.1.13. ref_clk for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - DDR4 Component
4.2. IP Interfaces for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - DDR5 Component x
4.2.1. s0_axi4_clock_in for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - DDR5 Component 4.2.2. s0_axi4_clock_out for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - DDR5 Component 4.2.3. s0_axi4_ctrl_ready for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - DDR5 Component 4.2.4. core_init_n for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - DDR5 Component 4.2.5. s0_axi4 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - DDR5 Component 4.2.6. s1_axi4 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - DDR5 Component 4.2.7. s0_axi4lite_clock for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - DDR5 Component 4.2.8. s0_axi4lite_reset_n for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - DDR5 Component 4.2.9. s0_axi4lite for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - DDR5 Component 4.2.10. mem_0 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - DDR5 Component 4.2.11. mem_ck_0 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - DDR5 Component 4.2.12. mem_reset_n_0 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - DDR5 Component 4.2.13. mem_1 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - DDR5 Component 4.2.14. mem_ck_1 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - DDR5 Component 4.2.15. mem_reset_n_1 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - DDR5 Component 4.2.16. oct_0 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - DDR5 Component 4.2.17. oct_1 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - DDR5 Component 4.2.18. ref_clk for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - DDR5 Component
4.3. IP Interfaces for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR4 x
4.3.1. s0_axi4_clock_in for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR4 4.3.2. core_init_n for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR4 4.3.3. s0_axi4_ctrl_ready for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR4 4.3.4. s0_axi4_clock_out for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR4 4.3.5. s1_axi4_ctrl_ready for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR4 4.3.6. s1_axi4_clock_out for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR4 4.3.7. s0_axi4 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR4 4.3.8. s1_axi4 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR4 4.3.9. s2_axi4 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR4 4.3.10. s3_axi4 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR4 4.3.11. s0_axi4lite_clock for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR4 4.3.12. s0_axi4lite_reset_n for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR4 4.3.13. s0_axi4lite for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR4 4.3.14. s1_axi4lite_clock for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR4 4.3.15. s1_axi4lite_reset_n for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR4 4.3.16. s1_axi4lite for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR4 4.3.17. mem_0 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR4 4.3.18. mem_ck_0 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR4 4.3.19. mem_1 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR4 4.3.20. mem_ck_1 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR4 4.3.21. mem_2 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR4 4.3.22. mem_ck_2 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR4 4.3.23. mem_3 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR4 4.3.24. mem_ck_3 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR4 4.3.25. mem_reset_n for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR4 4.3.26. oct_0 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR4 4.3.27. oct_1 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR4 4.3.28. oct_2 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR4 4.3.29. oct_3 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR4 4.3.30. ref_clk for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR4
4.4. IP Interfaces for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR5 x
4.4.1. s0_axi4_clock_in for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.4.2. core_init_n for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.4.3. s0_axi4_ctrl_ready for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.4.4. s0_axi4_clock_out for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.4.5. s1_axi4_ctrl_ready for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.4.6. s1_axi4_clock_out for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.4.7. s0_axi4 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.4.8. s1_axi4 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.4.9. s2_axi4 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.4.10. s3_axi4 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.4.11. s0_axi4lite_clock for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.4.12. s0_axi4lite_reset_n for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.4.13. s0_axi4lite for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.4.14. s1_axi4lite_clock for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.4.15. s1_axi4lite_reset_n for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.4.16. s1_axi4lite for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.4.17. mem_0 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.4.18. mem_ck_0 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.4.19. mem_1 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.4.20. mem_ck_1 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.4.21. mem_2 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.4.22. mem_ck_2 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.4.23. mem_3 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.4.24. mem_ck_3 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.4.25. mem_reset_n for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.4.26. oct_0 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.4.27. oct_1 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.4.28. oct_2 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.4.29. oct_3 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.4.30. ref_clk for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR5
5. Agilex™ 5 FPGA EMIF IP – Simulating Memory IP x
5.1. Simulation Walkthrough
5.1. Simulation Walkthrough x
5.1.1. Calibration 5.1.2. Simulation Scripts 5.1.3. Functional Simulation with Verilog HDL 5.1.4. Simulating the Design Example
6. Agilex™ 5 FPGA EMIF IP - DDR4 Support x
6.1. External Memory Interfaces (EMIF) IP - DDR4 Component Parameter Descriptions 6.2. External Memory Interfaces (EMIF) IP - DDR4 DIMM Parameter Descriptions 6.3. Agilex™ 5 FPGA EMIF IP Pin and Resource Planning 6.4. Agilex™ 5 EMIF Pin Swapping Guidelines
6.3. Agilex™ 5 FPGA EMIF IP Pin and Resource Planning x
6.3.1. Agilex™ 5 FPGA EMIF IP Resources 6.3.2. Pin Guidelines for Agilex™ 5 FPGA EMIF IP 6.3.3. Pin Placements for Agilex™ 5 FPGA DDR4 EMIF IP
6.3.1. Agilex™ 5 FPGA EMIF IP Resources x
6.3.1.1. OCT 6.3.1.2. PLL
6.3.2. Pin Guidelines for Agilex™ 5 FPGA EMIF IP x
6.3.2.1. Agilex™ 5 FPGA EMIF IP Pin and Resource Planning
6.3.2.1. Agilex™ 5 FPGA EMIF IP Pin and Resource Planning x
6.3.2.1.1. Agilex™ 5 FPGA EMIF IP Interface Pins 6.3.2.1.2. Estimating Pin Requirements 6.3.2.1.3. Maximum Number of Interfaces
6.3.3. Pin Placements for Agilex™ 5 FPGA DDR4 EMIF IP x
6.3.3.1. Address and Command Pin Placement for DDR4 6.3.3.2. DDR4 Data Width Mapping 6.3.3.3. Clamshell Topology 6.3.3.4. General Guidelines 6.3.3.5. x4 DIMM Implementation 6.3.3.6. Specific Pin Connection Requirements 6.3.3.7. Command and Address Signals 6.3.3.8. Clock Signals 6.3.3.9. Data, Data Strobes, DM/DBI, and Optional ECC Signals
6.4. Agilex™ 5 EMIF Pin Swapping Guidelines x
6.4.1. DDR4 Byte Lane Swapping 6.4.2. DDR4 Address and Command and CLK Lane 6.4.3. DDR4 Interface x8 Data Lane 6.4.4. DDR4 Interface x4 Data Lane
7. Agilex™ 5 FPGA EMIF IP - DDR5 Support x
7.1. External Memory Interfaces (EMIF) IP - DDR5 Component Parameter Descriptions 7.2. External Memory Interfaces (EMIF) IP - DDR5 DIMM Parameter Descriptions 7.3. Agilex™ 5 FPGA EMIF IP Pin and Resource Planning
7.3. Agilex™ 5 FPGA EMIF IP Pin and Resource Planning x
7.3.1. Agilex™ 5 FPGA EMIF IP Interface Pins 7.3.2. Agilex™ 5 FPGA EMIF IP Resources 7.3.3. Pin Guidelines for Agilex™ 5 FPGA EMIF IP 7.3.4. Pin Placements for Agilex™ 5 FPGA DDR5 EMIF IP 7.3.5. Agilex™ 5 EMIF Pin Swapping Guidelines
7.3.1. Agilex™ 5 FPGA EMIF IP Interface Pins x
7.3.1.1. Estimating Pin Requirements 7.3.1.2. DIMM Options 7.3.1.3. Maximum Number of Interfaces
7.3.2. Agilex™ 5 FPGA EMIF IP Resources x
7.3.2.1. OCT 7.3.2.2. PLL
7.3.3. Pin Guidelines for Agilex™ 5 FPGA EMIF IP x
7.3.3.1. General Guidelines - DDR5 7.3.3.2. x4 DIMM Implementation 7.3.3.3. Specific Pin Connection Requirements 7.3.3.4. Command and Address Signals 7.3.3.5. Clock Signals 7.3.3.6. Data, Data Strobes, DM, and Optional ECC Signals
7.3.4. Pin Placements for Agilex™ 5 FPGA DDR5 EMIF IP x
7.3.4.1. Address and Command Pin Placement for DDR5 7.3.4.2. DDR5 Data Width Mapping
7.3.5. Agilex™ 5 EMIF Pin Swapping Guidelines x
7.3.5.1. DDR5 Byte Lane Swapping 7.3.5.2. DDR5 Address and Command and CLK Lane 7.3.5.3. DDR5 Interface x8 Data Lane 7.3.5.4. DDR5 Interface x4 Data Lane 7.3.5.5. Pin Swizzling
8. Agilex™ 5 FPGA EMIF IP - LPDDR4 Support x
8.1. External Memory Interfaces (EMIF) IP - LPDDR4 Parameter Descriptions 8.2. Agilex™ 5 FPGA EMIF IP Pin and Resource Planning
8.2. Agilex™ 5 FPGA EMIF IP Pin and Resource Planning x
8.2.1. Agilex™ 5 FPGA EMIF IP Interface Pins 8.2.2. Agilex™ 5 FPGA EMIF IP Resources 8.2.3. Pin Guidelines for Agilex™ 5 FPGA EMIF IP
8.2.1. Agilex™ 5 FPGA EMIF IP Interface Pins x
8.2.1.1. Estimating Pin Requirements 8.2.1.2. LPDDR4 Component Options 8.2.1.3. Maximum Number of Interfaces
8.2.2. Agilex™ 5 FPGA EMIF IP Resources x
8.2.2.1. OCT 8.2.2.2. PLL
8.2.3. Pin Guidelines for Agilex™ 5 FPGA EMIF IP x
8.2.3.1. General Guidelines 8.2.3.2. Specific Pin Connection Requirements 8.2.3.3. Command and Address Signals 8.2.3.4. Clock Signals 8.2.3.5. Address and Command Pin Placement for LPDDR4 8.2.3.6. LPDDR4 Data Width Mapping 8.2.3.7. Pin Swapping Guidelines
9. Agilex™ 5 FPGA EMIF IP - LPDDR5 Support x
9.1. External Memory Interfaces (EMIF) IP - LPDDR5 Parameter Descriptions 9.2. Agilex™ 5 FPGA EMIF IP Pin and Resource Planning
9.2. Agilex™ 5 FPGA EMIF IP Pin and Resource Planning x
9.2.1. Agilex™ 5 FPGA EMIF IP Interface Pins 9.2.2. Agilex™ 5 FPGA EMIF IP Resources 9.2.3. Pin Guidelines for Agilex™ 5 FPGA EMIF IP 9.2.4. Pin Placements for Agilex™ 5 FPGA LPDDR5 EMIF IP
9.2.1. Agilex™ 5 FPGA EMIF IP Interface Pins x
9.2.1.1. Estimating Pin Requirements 9.2.1.2. LPDDR5 Component Options 9.2.1.3. Maximum Number of Interfaces
9.2.2. Agilex™ 5 FPGA EMIF IP Resources x
9.2.2.1. OCT 9.2.2.2. PLL
9.2.3. Pin Guidelines for Agilex™ 5 FPGA EMIF IP x
9.2.3.1. General Guidelines - LPDDR5 9.2.3.2. Specific Pin Connection Requirements 9.2.3.3. Command and Address Signals 9.2.3.4. Clock Signals
9.2.4. Pin Placements for Agilex™ 5 FPGA LPDDR5 EMIF IP x
9.2.4.1. Address and Command Pin Placement for LPDDR5 9.2.4.2. LPDDR5 Data Width Mapping 9.2.4.3. LPDDR5 Byte Lane Swapping
10. Agilex™ 5 FPGA EMIF IP – Timing Closure x
10.1. Timing Closure 10.2. Optimizing Timing
10.1. Timing Closure x
10.1.1. Timing Analysis
10.1.1. Timing Analysis x
10.1.1.1. PHY or Core
11. Agilex™ 5 FPGA EMIF IP – Controller Optimization x
11.1. Optimizing Efficiency for Secondary Controller 11.2. Interface Standard 11.3. Bank Management Efficiency 11.4. Data Transfer 11.5. Improving Controller Efficiency
11.5. Improving Controller Efficiency x
11.5.1. Frequency of Operation 11.5.2. Series of Reads or Writes 11.5.3. AXI to Memory Mapping
12. Agilex™ 5 FPGA EMIF IP – Debugging x
12.1. Interface Configuration Performance Issues 12.2. Functional Issue Evaluation 12.3. Timing Issue Characteristics 12.4. Verifying Memory IP Using the Signal Tap Logic Analyzer 12.5. Debugging with the External Memory Interface Debug Toolkit 12.6. Generating Traffic with the Test Engine IP 12.7. Guidelines for Developing HDL for Traffic Generator 12.8. Guidelines for Traffic Generator Status Check 12.9. Hardware Debugging Guidelines 12.10. Categorizing Hardware Issues
12.1. Interface Configuration Performance Issues x
12.1.1. Interface Configuration Bottleneck and Efficiency Issues
12.2. Functional Issue Evaluation x
12.2.1. Altera IP Memory Model 12.2.2. Vendor Memory Model 12.2.3. Transcript Window Messages
12.3. Timing Issue Characteristics x
12.3.1. Evaluating FPGA Timing Issues 12.3.2. Evaluating External Memory Interface Timing Issues
12.5. Debugging with the External Memory Interface Debug Toolkit x
12.5.1. Prerequisites for Using the EMIF Debug Toolkit 12.5.2. Configuring a Design to Use the Debug Toolkit 12.5.3. Launching the EMIF Debug Toolkit 12.5.4. Using the EMIF Debug Toolkit
12.5.2. Configuring a Design to Use the Debug Toolkit x
12.5.2.1. Generating a Design Example with the Debug Toolkit
12.5.4. Using the EMIF Debug Toolkit x
12.5.4.1. Running Re-Calibration 12.5.4.2. Running the Test Engine
12.8. Guidelines for Traffic Generator Status Check x
12.8.1. Status Check Using the Signal Tap Logic Analyzer 12.8.2. Exporting the Status Interface to the Top-Level Design
12.9. Hardware Debugging Guidelines x
12.9.1. Create a Simplified Design that Demonstrates the Same Issue 12.9.2. Measure Power Distribution Network 12.9.3. Measure Signal Integrity and Setup and Hold Margin 12.9.4. Vary Voltage 12.9.5. Operate at a Lower Speed 12.9.6. Determine Whether the Issue Exists in Previous Versions of Software 12.9.7. Determine Whether the Issue Exists in the Current Version of Software 12.9.8. Try A Different PCB 12.9.9. Try Other Configurations 12.9.10. Debugging Checklist
12.10. Categorizing Hardware Issues x
12.10.1. Signal Integrity Issues 12.10.2. Hardware and Calibration Issues
12.10.1. Signal Integrity Issues x
12.10.1.1. Characteristics of Signal Integrity Issues 12.10.1.2. Evaluating Signal Integrity Issues 12.10.1.3. Skew 12.10.1.4. Crosstalk 12.10.1.5. Power System 12.10.1.6. Clock Signals 12.10.1.7. Address and Command Signals 12.10.1.8. Read Data Valid Window and Eye Diagram 12.10.1.9. Write Data Valid Window and Eye Diagram
12.10.2. Hardware and Calibration Issues x
12.10.2.1. Verifying High-Level Configuration 12.10.2.2. Verifying Memory Timing Parameters 12.10.2.3. Verifying the Correct Memory Component or DIMM Installed 12.10.2.4. Debugging Intermittent Issues
13. Agilex™ 5 FPGA EMIF IP - Mailbox Support x
13.1. Agilex™ 5 Mailbox Structure and Register Definitions 13.2. Accessing Read-Only Registers 13.3. Sending a Mailbox Command 13.4. IOSSM Mailbox Access Script
13.1. Agilex™ 5 Mailbox Structure and Register Definitions x
13.1.1. Mailbox Supported Commands 13.1.2. Mailbox Command Definitions 13.1.3. ECC Syndrome Codes 13.1.4. ECC Error Handling
13.2. Accessing Read-Only Registers x
13.2.1. Example 1: Reading IP_TYPE and IP_INSTANCE_ID of All the Interfaces in the IO96B Through Read-Only Registers 13.2.2. Example 2: Reading the Memory Clock Frequency for an Interface
13.3. Sending a Mailbox Command x
13.3.1. Example 3: Sending Recalibration Request and Reading Calibration Status Using the Mailbox
13.3.1. Example 3: Sending Recalibration Request and Reading Calibration Status Using the Mailbox x
13.3.1.1. Example 4: Sending ECC_INJECT_ERROR Using the Mailbox and Reading ECC Error Status, ECC Error Buffer Registers
13.4. IOSSM Mailbox Access Script x
13.4.1. Mailbox Script Overview 13.4.2. Running the Mailbox Script
13.4.1. Mailbox Script Overview x
13.4.1.1. mb_iossm_command.tcl 13.4.1.2. mb_user_input.tcl
1. About the External Memory Interfaces Agilex™ 5 FPGA IP
2. Agilex™ 5 FPGA EMIF IP – Introduction
3. Agilex™ 5 FPGA EMIF IP – Product Architecture
4. Agilex™ 5 FPGA EMIF IP – End-User Signals
5. Agilex™ 5 FPGA EMIF IP – Simulating Memory IP
6. Agilex™ 5 FPGA EMIF IP - DDR4 Support
7. Agilex™ 5 FPGA EMIF IP - DDR5 Support
8. Agilex™ 5 FPGA EMIF IP - LPDDR4 Support
9. Agilex™ 5 FPGA EMIF IP - LPDDR5 Support
10. Agilex™ 5 FPGA EMIF IP – Timing Closure
11. Agilex™ 5 FPGA EMIF IP – Controller Optimization
12. Agilex™ 5 FPGA EMIF IP – Debugging
13. Agilex™ 5 FPGA EMIF IP - Mailbox Support
14. Document Revision History for External Memory Interfaces (EMIF) IP User Guide

3.5. Agilex™ 5 EMIF IP for Hard Processor Subsystem (HPS)

The Agilex™ 5 FPGA EMIF IP can enable the Agilex™ 5 FPGA hard processor subsystem (HPS) to access external DRAM memory devices.

To enable connectivity between the HPS and the Agilex™ 5 EMIF IP, you must create and configure an instance of the EMIF for HPS IP, and connect it to the Agilex™ 5 FPGA hard processor subsystem instance in your system.

HPS EMIF Mapping (Both bridges are used)

When using both the F2H bridge and the F2SDRAM bridge, no I/O sharing is allowed. That is, the HPS can access DDR and fabric can access DDR via the F2H and/or F2SDRAM bridge, but no GPIO, etc is allowed.

Table 22.  HPS EMIF Mapping (Both bridges are used)
Protocol Banks Data Width BL7 BL6 BL5 BL4 BL3 BL2 BL1 BL0
DDR4 1 1x16 X X X DQ[1] AC2 AC1 AC0 DQ[0]
1 1x16+ECC X X DQ[ECC] DQ[1] AC2 AC1 AC0 DQ[0]
1 or 2 1x32 X DQ[3] DQ[2] DQ[1] AC2 AC1 AC0 DQ[0]
1 or 2 1x32+ECC DQ[ECC] DQ[3] DQ[2] DQ[1] AC2 AC1 AC0 DQ[0]
1 1x16 DQ[0] AC0 AC2 AC1 DQ[1] X X X
1 1x16+ECC DQ[0] AC0 AC2 AC1 DQ[1] DQ[ECC] X X
1 or 2 1x32 DQ[0] AC0 AC2 AC1 DQ[1] DQ[2] DQ[3] X
1 or 2 1x32+ECC DQ[0] AC0 AC2 AC1 DQ[1] DQ[2] DQ[3] DQ[ECC]
N/A 1x64 Not supported
N/A 1x64+ECC Not supported
DDR5 1 1x16 X X X X AC1 AC0 DQ[0] DQ[1]
1 1x16+ECC X X X DQ[ECC] AC1 AC0 DQ[0] DQ[1]
1 or 2 1x32 X X DQ[3] DQ[2] AC1 AC0 DQ[0] DQ[1]
1 or 2 1x32+ECC X DQ[ECC] DQ[3] DQ[2] AC1 AC0 DQ[0] DQ[1]
1 1x16 DQ[1] DQ[0] AC1 AC0 X X X X
1 1x16+ECC DQ[1] DQ[0] AC1 AC0 DQ[ECC] X X X
1 or 2 1x32 DQ[1] DQ[0] AC1 AC0 DQ[2] DQ[3] X X
1 or 2 1x32+ECC DQ[1] DQ[0] AC1 AC0 DQ[2] DQ[3] DQ[ECC] X
1 2x16 DQ[1] DQ[0] AC1 AC0 AC1 AC0 DQ[0] DQ[1]
LPDDR4 / LPDDR5 1 1x16 X X X X AC1 AC0 DQ[1] DQ[0]
1 or 2 1x32 DQ[3] DQ[2] X X AC1 AC0 DQ[1] DQ[0]
1 2x16 DQ[1] DQ[0] AC1 AC0 AC1 AC0 DQ[1] DQ[0]
2 4x16 DQ[1] DQ[0] AC1 AC0 AC1 AC0 DQ[1] DQ[0]
  • GM - Available for GPIO, MIPI, LVDS SERDES, or PHYLite..
  • GL - Available for GPIO or LVDS SERDES (no RZQ free). Can support MIPI through RZQ sharing.
  • GO - Available for GPIO only (no refclk lane free). Can support MIPI through RZQ and refclk sharing.
  • RZ - RZQ and refclk lane when using PHYLite/MIPI.
  • X - Not Available.

HPS EMIF Mapping (Using only the F2SDRAM bridge)

The following table shows the I/O sharing that is allowed when using the F2SDRAM bridge and not using the F2H bridge. The HPS can access DDR and fabric can access DDR via the F2SDRAM bridge only.

Table 23.  HPS EMIF Mapping (Using only the F2SDRAM bridge)
Protocol Banks Data Width BL7 BL6 BL5 BL4 BL3 BL2 BL1 BL0
DDR4 1 1x16 GM GM RZ DQ[1] AC2 AC1 AC0 DQ[0]
1 1x16+ECC GO GO DQ[ECC] DQ[1] AC2 AC1 AC0 DQ[0]
1 or 2 1x32 GO DQ[3] DQ[2] DQ[1] AC2 AC1 AC0 DQ[0]
1 or 2 1x32+ECC DQ[ECC] DQ[3] DQ[2] DQ[1] AC2 AC1 AC0 DQ[0]
1 1x16 DQ[0] AC0 AC2 AC1 DQ[1] X X X
1 1x16+ECC DQ[0] AC0 AC2 AC1 DQ[1] DQ[ECC] X X
1 or 2 1x32 DQ[0] AC0 AC2 AC1 DQ[1] DQ[2] DQ[3] X
1 or 2 1x32+ECC DQ[0] AC0 AC2 AC1 DQ[1] DQ[2] DQ[3] DQ[ECC]
N/A 1x64 Not supported
N/A 1x64+ECC Not supported
DDR5 1 1x16 GM GM RZ GM AC1 AC0 DQ[0] DQ[1]
1 1x16+ECC GM GM RZ DQ[ECC] AC1 AC0 DQ[0] DQ[1]
1 or 2 1x32 GO GO DQ[3] DQ[2] AC1 AC0 DQ[0] DQ[1]
1 or 2 1x32+ECC GO DQ[ECC] DQ[3] DQ[2] AC1 AC0 DQ[0] DQ[1]
1 1x16 DQ[1] DQ[0] AC1 AC0 X X X X
1 1x16+ECC DQ[1] DQ[0] AC1 AC0 DQ[ECC] X X X
1 or 2 1x32 DQ[1] DQ[0] AC1 AC0 DQ[2] DQ[3] X X
1 or 2 1x32+ECC DQ[1] DQ[0] AC1 AC0 DQ[2] DQ[3] DQ[ECC] X
1 2x16 DQ[1] DQ[0] AC1 AC0 AC1 AC0 DQ[0] DQ[1]
LPDDR4 / LPDDR5 1 1x16 GM GM RZ GM AC1 AC0 DQ[1] DQ[0]
1 or 2 1x32 DQ[3] DQ[2] RZ GM AC1 AC0 DQ[1] DQ[0]
1 2x16 DQ[1] DQ[0] AC1 AC0 AC1 AC0 DQ[1] DQ[0]
2 4x16 DQ[1] DQ[0] AC1 AC0 AC1 AC0 DQ[1] DQ[0]
  • GM - Available for GPIO, MIPI, LVDS SERDES, or PHYLite..
  • GL - Available for GPIO or LVDS SERDES (no RZQ free). Can support MIPI through RZQ sharing.
  • GO - Available for GPIO only (no refclk lane free). Can support MIPI through RZQ and refclk sharing.
  • RZ - RZQ and refclk lane when using PHYLite/MIPI.
  • X - Not Available.

HPS EMIF Mapping (Using only the F2H bridge)

The following table shows the I/O sharing permitted when using the F2H bridge and not using the F2SDRAM bridge. The HPS can access DDR and fabric can access DDR via the F2H bridge only.

Table 24.  HPS EMIF Mapping (Using only the F2H bridge)
Protocol Banks Data Width BL7 BL6 BL5 BL4 BL3 BL2 BL1 BL0
DDR4 1 1x16 X X X DQ[1] AC2 AC1 AC0 DQ[0]
1 1x16+ECC X X DQ[ECC] DQ[1] AC2 AC1 AC0 DQ[0]
1 or 2 1x32 X DQ[3] DQ[2] DQ[1] AC2 AC1 AC0 DQ[0]
1 or 2 1x32+ECC DQ[ECC] DQ[3] DQ[2] DQ[1] AC2 AC1 AC0 DQ[0]
1 1x16 DQ[0] AC0 AC2 AC1 DQ[1] GL GL GL
1 1x16+ECC DQ[0] AC0 AC2 AC1 DQ[1] DQ[ECC] GO GO
1 or 2 1x32 DQ[0] AC0 AC2 AC1 DQ[1] DQ[2] DQ[3] GO
1 or 2 1x32+ECC DQ[0] AC0 AC2 AC1 DQ[1] DQ[2] DQ[3] DQ[ECC]
N/A 1x64 Not supported
N/A 1x64+ECC Not supported
DDR5 1 1x16 X X X X AC1 AC0 DQ[0] DQ[1]
1 1x16+ECC X X X DQ[ECC] AC1 AC0 DQ[0] DQ[1]
1 or 2 1x32 X X DQ[3] DQ[2] AC1 AC0 DQ[0] DQ[1]
1 or 2 1x32+ECC X DQ[ECC] DQ[3] DQ[2] AC1 AC0 DQ[0] DQ[1]
1 1x16 DQ[1] DQ[0] AC1 AC0 RZ GM GM GM
1 1x16+ECC DQ[1] DQ[0] AC1 AC0 DQ[ECC] GL GL GL
1 or 2 1x32 DQ[1] DQ[0] AC1 AC0 DQ[2] DQ[3] GO GO
1 or 2 1x32+ECC DQ[1] DQ[0] AC1 AC0 DQ[2] DQ[3] DQ[ECC] GO
1 2x16 DQ[1] DQ[0] AC1 AC0 AC1 AC0 DQ[0] DQ[1]
LPDDR4 / LPDDR5 1 1x16 X X X X AC1 AC0 DQ[1] DQ[0]
1 or 2 1x32 DQ[3] DQ[2] X X AC1 AC0 DQ[1] DQ[0]
1 2x16 DQ[1] DQ[0] AC1 AC0 AC1 AC0 DQ[1] DQ[0]
2 4x16 DQ[1] DQ[0] AC1 AC0 AC1 AC0 DQ[1] DQ[0]
  • GM - Available for GPIO, MIPI, LVDS SERDES, or PHYLite..
  • GL - Available for GPIO or LVDS SERDES (no RZQ free). Can support MIPI through RZQ sharing.
  • GO - Available for GPIO only (no refclk lane free). Can support MIPI through RZQ and refclk sharing.
  • RZ - RZQ and refclk lane when using PHYLite/MIPI.
  • X - Not Available.

HPS EMIF Mapping (No bridges are used)

The following table shows the I/O sharing permitted when using neither the F2H bridge nor the FS2DRAM bridge. The HPS can access DDR, but the fabric cannot.

Table 25.  HPS EMIF Mapping (No bridges are used)
Protocol Banks Data Width BL7 BL6 BL5 BL4 BL3 BL2 BL1 BL0
DDR4 1 1x16 GM GM RZ DQ[1] AC2 AC1 AC0 DQ[0]
1 1x16+ECC GO GO DQ[ECC] DQ[1] AC2 AC1 AC0 DQ[0]
1 or 2 1x32 GO DQ[3] DQ[2] DQ[1] AC2 AC1 AC0 DQ[0]
1 or 2 1x32+ECC DQ[ECC] DQ[3] DQ[2] DQ[1] AC2 AC1 AC0 DQ[0]
1 1x16 DQ[0] AC0 AC2 AC1 DQ[1] GL GL GL
1 1x16+ECC DQ[0] AC0 AC2 AC1 DQ[1] DQ[ECC] GO GO
1 or 2 1x32 DQ[0] AC0 AC2 AC1 DQ[1] DQ[2] DQ[3] GO
1 or 2 1x32+ECC DQ[0] AC0 AC2 AC1 DQ[1] DQ[2] DQ[3] DQ[ECC]
N/A 1x64 Not supported
N/A 1x64+ECC Not supported
DDR5 1 1x16 GM GM RZ GM AC1 AC0 DQ[0] DQ[1]
1 1x16+ECC GM GM RZ DQ[ECC] AC1 AC0 DQ[0] DQ[1]
1 or 2 1x32 GO GO DQ[3] DQ[2] AC1 AC0 DQ[0] DQ[1]
1 or 2 1x32+ECC GO DQ[ECC] DQ[3] DQ[2] AC1 AC0 DQ[0] DQ[1]
1 1x16 DQ[1] DQ[0] AC1 AC0 RZ GM GM GM
1 1x16+ECC DQ[1] DQ[0] AC1 AC0 DQ[ECC] GL GL GL
1 or 2 1x32 DQ[1] DQ[0] AC1 AC0 DQ[2] DQ[3] GO GO
1 or 2 1x32+ECC DQ[1] DQ[0] AC1 AC0 DQ[2] DQ[3] DQ[ECC] GO
1 2x16 DQ[1] DQ[0] AC1 AC0 AC1 AC0 DQ[0] DQ[1]
LPDDR4 / LPDDR5 1 1x16 GM GM RZ GM AC1 AC0 DQ[1] DQ[0]
1 or 2 1x32 DQ[3] DQ[2] RZ GM AC1 AC0 DQ[1] DQ[0]
1 2x16 DQ[1] DQ[0] AC1 AC0 AC1 AC0 DQ[1] DQ[0]
2 4x16 DQ[1] DQ[0] AC1 AC0 AC1 AC0 DQ[1] DQ[0]
  • GM - Available for GPIO, MIPI, LVDS SERDES, or PHYLite..
  • GL - Available for GPIO or LVDS SERDES (no RZQ free). Can support MIPI through RZQ sharing.
  • GO - Available for GPIO only (no refclk lane free). Can support MIPI through RZQ and refclk sharing.
  • RZ - RZQ and refclk lane when using PHYLite/MIPI.
  • X - Not Available.

I/O Sharing versus HPS EMIF DDR Protocol versus Bridge Allowed

The following table summarizes the information from the previous tables, showing which bridge can be used with which I/O sharing and DDR protocol combinations.

Table 26.  I/O Sharing versus HPS EMIF DDR Protocol versus Bridge Allowed
I/O Sharing Protocol Banks Data Width Bridge Allowed
MIPI or PHYLite DDR4 1 1x16 F2SDRAM
DDR4 1 1x16 F2SDRAM or F2H
1 1x16+ECC F2SDRAM
LPDDR4 / LPDDR5 1 1x16 F2SDRAM
1 or 2 1x32 F2SDRAM
MIPI through RZQ sharing DDR4 1 1x16 F2H
DDR5 1 1x16+ECC F2H
MIPI through RZQ and refclk sharing DDR4 1 1x16+ECC F2SDRAM or F2H
1 or 2 1x32 F2SDRAM or F2H
DDR5 1 or 2 1x32 F2SDRAM or F2H
1 or 2 1x32+ECC F2SDRAM or F2H
LVDS DDR4 1 1x16 F2SDRAM or F2H
DDR5 1 1x16 F2SDRAM or F2H
1 1x16+ECC F2SDRAM or F2H
LPDDR4 / LPDDR5 1 1x16 F2SDRAM
1 or 2 1x32 F2SDRAM
GPIO DDR4 1 1x16 F2SDRAM or F2H
1 1x16+ECC F2SDRAM or F2H
1 or 2 1x32 F2SDRAM or F2H
DDR5 1 1x16 F2SDRAM or F2H
1 1x16+ECC F2SDRAM or F2H
1 or 2 1x32 F2SDRAM or F2H
1 or 2 1x32+ECC F2SDRAM or F2H
LPDDR4 / LPDDR5 1 1x16 F2SDRAM
1 or 2 1x32 F2SDRAM

Section Content
Restrictions on I/O Bank Usage for EMIF IP with HPS
Using the Legacy EMIF Debug Toolkit with Agilex 5 HPS Interfaces

Level Two Title