External Memory Interfaces (EMIF) IP User Guide: Agilex™ 5 FPGAs and SoCs

ID 817467
Date 3/31/2025
Public
Document Table of Contents

4.2.15. mem_reset_n_1 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - DDR5 Component

Reset pin to the memory (channel 1).

Table 56.  Interface: mem_reset_n_1Interface type: conduit
Port Name Direction Description
mem_1_reset_n Output Asynchronous Reset channel 1.