External Memory Interfaces (EMIF) IP User Guide: Agilex™ 5 FPGAs and SoCs

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ID 817467
Date 3/31/2025
Public
Document Table of Contents
Document Table of Contents x
1. About the External Memory Interfaces Agilex™ 5 FPGA IP 2. Agilex™ 5 FPGA EMIF IP – Introduction 3. Agilex™ 5 FPGA EMIF IP – Product Architecture 4. Agilex™ 5 FPGA EMIF IP – End-User Signals 5. Agilex™ 5 FPGA EMIF IP – Simulating Memory IP 6. Agilex™ 5 FPGA EMIF IP - DDR4 Support 7. Agilex™ 5 FPGA EMIF IP - DDR5 Support 8. Agilex™ 5 FPGA EMIF IP - LPDDR4 Support 9. Agilex™ 5 FPGA EMIF IP - LPDDR5 Support 10. Agilex™ 5 FPGA EMIF IP – Timing Closure 11. Agilex™ 5 FPGA EMIF IP – Controller Optimization 12. Agilex™ 5 FPGA EMIF IP – Debugging 13. Agilex™ 5 FPGA EMIF IP - Mailbox Support 14. Document Revision History for External Memory Interfaces (EMIF) IP User Guide
1. About the External Memory Interfaces Agilex™ 5 FPGA IP x
1.1. Release Information
2. Agilex™ 5 FPGA EMIF IP – Introduction x
2.1. Agilex™ 5 EMIF IP Protocol and Feature Support 2.2. Agilex™ 5 EMIF IP Design Flow
2.2. Agilex™ 5 EMIF IP Design Flow x
2.2.1. Agilex™ 5 EMIF IP Design Checklist
3. Agilex™ 5 FPGA EMIF IP – Product Architecture x
3.1. Agilex™ 5 EMIF Architecture: Protocol and Maximum Interface Width Support 3.2. Agilex™ 5 EMIF Architecture: Introduction 3.3. Agilex™ 5 EMIF Sequencer 3.4. Agilex™ 5 EMIF Controller 3.5. Agilex™ 5 EMIF IP for Hard Processor Subsystem (HPS)
3.2. Agilex™ 5 EMIF Architecture: Introduction x
3.2.1. Agilex™ 5 EMIF Architecture: I/O Subsystem 3.2.2. Agilex™ 5 EMIF Architecture: I/O SSM 3.2.3. Agilex™ 5 EMIF Architecture: HSIO Bank 3.2.4. Agilex™ 5 EMIF Architecture: I/O Lane 3.2.5. Agilex™ 5 EMIF Architecture: Input DQS Clock Tree 3.2.6. Agilex™ 5 EMIF Architecture: PHY Clock Tree 3.2.7. Agilex™ 5 EMIF Architecture: PLL Reference Clock Networks 3.2.8. Agilex™ 5 EMIF Architecture: Clock Phase Alignment 3.2.9. User Clock in Different Core Access Modes
3.2.3. Agilex™ 5 EMIF Architecture: HSIO Bank x
3.2.3.1. Lockstep Configuration 3.2.3.2. Pin Placement 3.2.3.3. HSIO Sub-Bank Usage
3.4. Agilex™ 5 EMIF Controller x
3.4.1. Hard Memory Controller
3.4.1. Hard Memory Controller x
3.4.1.1. Hard Memory Controller Features
3.5. Agilex™ 5 EMIF IP for Hard Processor Subsystem (HPS) x
3.5.1. Restrictions on I/O Bank Usage for EMIF IP with HPS 3.5.2. Using the Legacy EMIF Debug Toolkit with Agilex 5 HPS Interfaces
4. Agilex™ 5 FPGA EMIF IP – End-User Signals x
4.1. IP Interfaces for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - DDR4 Component 4.2. IP Interfaces for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - DDR5 Component 4.3. IP Interfaces for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR4 4.4. IP Interfaces for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR5
4.1. IP Interfaces for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - DDR4 Component x
4.1.1. s0_axi4_clock_in for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - DDR4 Component 4.1.2. s0_axi4_clock_out for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - DDR4 Component 4.1.3. s0_axi4_ctrl_ready for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - DDR4 Component 4.1.4. core_init_n for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - DDR4 Component 4.1.5. s0_axi4 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - DDR4 Component 4.1.6. s0_axi4lite_clock for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - DDR4 Component 4.1.7. s0_axi4lite_reset_n for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - DDR4 Component 4.1.8. s0_axi4lite for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - DDR4 Component 4.1.9. mem_0 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - DDR4 Component 4.1.10. mem_ck_0 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - DDR4 Component 4.1.11. mem_reset_n for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - DDR4 Component 4.1.12. oct_0 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - DDR4 Component 4.1.13. ref_clk for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - DDR4 Component
4.2. IP Interfaces for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - DDR5 Component x
4.2.1. s0_axi4_clock_in for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - DDR5 Component 4.2.2. s0_axi4_clock_out for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - DDR5 Component 4.2.3. s0_axi4_ctrl_ready for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - DDR5 Component 4.2.4. core_init_n for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - DDR5 Component 4.2.5. s0_axi4 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - DDR5 Component 4.2.6. s1_axi4 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - DDR5 Component 4.2.7. s0_axi4lite_clock for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - DDR5 Component 4.2.8. s0_axi4lite_reset_n for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - DDR5 Component 4.2.9. s0_axi4lite for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - DDR5 Component 4.2.10. mem_0 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - DDR5 Component 4.2.11. mem_ck_0 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - DDR5 Component 4.2.12. mem_reset_n_0 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - DDR5 Component 4.2.13. mem_1 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - DDR5 Component 4.2.14. mem_ck_1 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - DDR5 Component 4.2.15. mem_reset_n_1 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - DDR5 Component 4.2.16. oct_0 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - DDR5 Component 4.2.17. oct_1 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - DDR5 Component 4.2.18. ref_clk for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - DDR5 Component
4.3. IP Interfaces for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR4 x
4.3.1. s0_axi4_clock_in for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR4 4.3.2. core_init_n for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR4 4.3.3. s0_axi4_ctrl_ready for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR4 4.3.4. s0_axi4_clock_out for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR4 4.3.5. s1_axi4_ctrl_ready for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR4 4.3.6. s1_axi4_clock_out for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR4 4.3.7. s0_axi4 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR4 4.3.8. s1_axi4 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR4 4.3.9. s2_axi4 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR4 4.3.10. s3_axi4 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR4 4.3.11. s0_axi4lite_clock for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR4 4.3.12. s0_axi4lite_reset_n for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR4 4.3.13. s0_axi4lite for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR4 4.3.14. s1_axi4lite_clock for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR4 4.3.15. s1_axi4lite_reset_n for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR4 4.3.16. s1_axi4lite for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR4 4.3.17. mem_0 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR4 4.3.18. mem_ck_0 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR4 4.3.19. mem_1 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR4 4.3.20. mem_ck_1 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR4 4.3.21. mem_2 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR4 4.3.22. mem_ck_2 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR4 4.3.23. mem_3 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR4 4.3.24. mem_ck_3 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR4 4.3.25. mem_reset_n for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR4 4.3.26. oct_0 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR4 4.3.27. oct_1 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR4 4.3.28. oct_2 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR4 4.3.29. oct_3 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR4 4.3.30. ref_clk for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR4
4.4. IP Interfaces for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR5 x
4.4.1. s0_axi4_clock_in for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.4.2. core_init_n for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.4.3. s0_axi4_ctrl_ready for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.4.4. s0_axi4_clock_out for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.4.5. s1_axi4_ctrl_ready for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.4.6. s1_axi4_clock_out for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.4.7. s0_axi4 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.4.8. s1_axi4 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.4.9. s2_axi4 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.4.10. s3_axi4 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.4.11. s0_axi4lite_clock for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.4.12. s0_axi4lite_reset_n for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.4.13. s0_axi4lite for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.4.14. s1_axi4lite_clock for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.4.15. s1_axi4lite_reset_n for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.4.16. s1_axi4lite for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.4.17. mem_0 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.4.18. mem_ck_0 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.4.19. mem_1 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.4.20. mem_ck_1 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.4.21. mem_2 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.4.22. mem_ck_2 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.4.23. mem_3 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.4.24. mem_ck_3 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.4.25. mem_reset_n for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.4.26. oct_0 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.4.27. oct_1 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.4.28. oct_2 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.4.29. oct_3 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.4.30. ref_clk for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR5
5. Agilex™ 5 FPGA EMIF IP – Simulating Memory IP x
5.1. Simulation Walkthrough
5.1. Simulation Walkthrough x
5.1.1. Calibration 5.1.2. Simulation Scripts 5.1.3. Functional Simulation with Verilog HDL 5.1.4. Simulating the Design Example
6. Agilex™ 5 FPGA EMIF IP - DDR4 Support x
6.1. External Memory Interfaces (EMIF) IP - DDR4 Component Parameter Descriptions 6.2. External Memory Interfaces (EMIF) IP - DDR4 DIMM Parameter Descriptions 6.3. Agilex™ 5 FPGA EMIF IP Pin and Resource Planning 6.4. Agilex™ 5 EMIF Pin Swapping Guidelines
6.3. Agilex™ 5 FPGA EMIF IP Pin and Resource Planning x
6.3.1. Agilex™ 5 FPGA EMIF IP Resources 6.3.2. Pin Guidelines for Agilex™ 5 FPGA EMIF IP 6.3.3. Pin Placements for Agilex™ 5 FPGA DDR4 EMIF IP
6.3.1. Agilex™ 5 FPGA EMIF IP Resources x
6.3.1.1. OCT 6.3.1.2. PLL
6.3.2. Pin Guidelines for Agilex™ 5 FPGA EMIF IP x
6.3.2.1. Agilex™ 5 FPGA EMIF IP Pin and Resource Planning
6.3.2.1. Agilex™ 5 FPGA EMIF IP Pin and Resource Planning x
6.3.2.1.1. Agilex™ 5 FPGA EMIF IP Interface Pins 6.3.2.1.2. Estimating Pin Requirements 6.3.2.1.3. Maximum Number of Interfaces
6.3.3. Pin Placements for Agilex™ 5 FPGA DDR4 EMIF IP x
6.3.3.1. Address and Command Pin Placement for DDR4 6.3.3.2. DDR4 Data Width Mapping 6.3.3.3. Clamshell Topology 6.3.3.4. General Guidelines 6.3.3.5. x4 DIMM Implementation 6.3.3.6. Specific Pin Connection Requirements 6.3.3.7. Command and Address Signals 6.3.3.8. Clock Signals 6.3.3.9. Data, Data Strobes, DM/DBI, and Optional ECC Signals
6.4. Agilex™ 5 EMIF Pin Swapping Guidelines x
6.4.1. DDR4 Byte Lane Swapping 6.4.2. DDR4 Address and Command and CLK Lane 6.4.3. DDR4 Interface x8 Data Lane 6.4.4. DDR4 Interface x4 Data Lane
7. Agilex™ 5 FPGA EMIF IP - DDR5 Support x
7.1. External Memory Interfaces (EMIF) IP - DDR5 Component Parameter Descriptions 7.2. External Memory Interfaces (EMIF) IP - DDR5 DIMM Parameter Descriptions 7.3. Agilex™ 5 FPGA EMIF IP Pin and Resource Planning
7.3. Agilex™ 5 FPGA EMIF IP Pin and Resource Planning x
7.3.1. Agilex™ 5 FPGA EMIF IP Interface Pins 7.3.2. Agilex™ 5 FPGA EMIF IP Resources 7.3.3. Pin Guidelines for Agilex™ 5 FPGA EMIF IP 7.3.4. Pin Placements for Agilex™ 5 FPGA DDR5 EMIF IP 7.3.5. Agilex™ 5 EMIF Pin Swapping Guidelines
7.3.1. Agilex™ 5 FPGA EMIF IP Interface Pins x
7.3.1.1. Estimating Pin Requirements 7.3.1.2. DIMM Options 7.3.1.3. Maximum Number of Interfaces
7.3.2. Agilex™ 5 FPGA EMIF IP Resources x
7.3.2.1. OCT 7.3.2.2. PLL
7.3.3. Pin Guidelines for Agilex™ 5 FPGA EMIF IP x
7.3.3.1. General Guidelines - DDR5 7.3.3.2. x4 DIMM Implementation 7.3.3.3. Specific Pin Connection Requirements 7.3.3.4. Command and Address Signals 7.3.3.5. Clock Signals 7.3.3.6. Data, Data Strobes, DM, and Optional ECC Signals
7.3.4. Pin Placements for Agilex™ 5 FPGA DDR5 EMIF IP x
7.3.4.1. Address and Command Pin Placement for DDR5 7.3.4.2. DDR5 Data Width Mapping
7.3.5. Agilex™ 5 EMIF Pin Swapping Guidelines x
7.3.5.1. DDR5 Byte Lane Swapping 7.3.5.2. DDR5 Address and Command and CLK Lane 7.3.5.3. DDR5 Interface x8 Data Lane 7.3.5.4. DDR5 Interface x4 Data Lane 7.3.5.5. Pin Swizzling
8. Agilex™ 5 FPGA EMIF IP - LPDDR4 Support x
8.1. External Memory Interfaces (EMIF) IP - LPDDR4 Parameter Descriptions 8.2. Agilex™ 5 FPGA EMIF IP Pin and Resource Planning
8.2. Agilex™ 5 FPGA EMIF IP Pin and Resource Planning x
8.2.1. Agilex™ 5 FPGA EMIF IP Interface Pins 8.2.2. Agilex™ 5 FPGA EMIF IP Resources 8.2.3. Pin Guidelines for Agilex™ 5 FPGA EMIF IP
8.2.1. Agilex™ 5 FPGA EMIF IP Interface Pins x
8.2.1.1. Estimating Pin Requirements 8.2.1.2. LPDDR4 Component Options 8.2.1.3. Maximum Number of Interfaces
8.2.2. Agilex™ 5 FPGA EMIF IP Resources x
8.2.2.1. OCT 8.2.2.2. PLL
8.2.3. Pin Guidelines for Agilex™ 5 FPGA EMIF IP x
8.2.3.1. General Guidelines 8.2.3.2. Specific Pin Connection Requirements 8.2.3.3. Command and Address Signals 8.2.3.4. Clock Signals 8.2.3.5. Address and Command Pin Placement for LPDDR4 8.2.3.6. LPDDR4 Data Width Mapping 8.2.3.7. Pin Swapping Guidelines
9. Agilex™ 5 FPGA EMIF IP - LPDDR5 Support x
9.1. External Memory Interfaces (EMIF) IP - LPDDR5 Parameter Descriptions 9.2. Agilex™ 5 FPGA EMIF IP Pin and Resource Planning
9.2. Agilex™ 5 FPGA EMIF IP Pin and Resource Planning x
9.2.1. Agilex™ 5 FPGA EMIF IP Interface Pins 9.2.2. Agilex™ 5 FPGA EMIF IP Resources 9.2.3. Pin Guidelines for Agilex™ 5 FPGA EMIF IP 9.2.4. Pin Placements for Agilex™ 5 FPGA LPDDR5 EMIF IP
9.2.1. Agilex™ 5 FPGA EMIF IP Interface Pins x
9.2.1.1. Estimating Pin Requirements 9.2.1.2. LPDDR5 Component Options 9.2.1.3. Maximum Number of Interfaces
9.2.2. Agilex™ 5 FPGA EMIF IP Resources x
9.2.2.1. OCT 9.2.2.2. PLL
9.2.3. Pin Guidelines for Agilex™ 5 FPGA EMIF IP x
9.2.3.1. General Guidelines - LPDDR5 9.2.3.2. Specific Pin Connection Requirements 9.2.3.3. Command and Address Signals 9.2.3.4. Clock Signals
9.2.4. Pin Placements for Agilex™ 5 FPGA LPDDR5 EMIF IP x
9.2.4.1. Address and Command Pin Placement for LPDDR5 9.2.4.2. LPDDR5 Data Width Mapping 9.2.4.3. LPDDR5 Byte Lane Swapping
10. Agilex™ 5 FPGA EMIF IP – Timing Closure x
10.1. Timing Closure 10.2. Optimizing Timing
10.1. Timing Closure x
10.1.1. Timing Analysis
10.1.1. Timing Analysis x
10.1.1.1. PHY or Core
11. Agilex™ 5 FPGA EMIF IP – Controller Optimization x
11.1. Optimizing Efficiency for Secondary Controller 11.2. Interface Standard 11.3. Bank Management Efficiency 11.4. Data Transfer 11.5. Improving Controller Efficiency
11.5. Improving Controller Efficiency x
11.5.1. Frequency of Operation 11.5.2. Series of Reads or Writes 11.5.3. AXI to Memory Mapping
12. Agilex™ 5 FPGA EMIF IP – Debugging x
12.1. Interface Configuration Performance Issues 12.2. Functional Issue Evaluation 12.3. Timing Issue Characteristics 12.4. Verifying Memory IP Using the Signal Tap Logic Analyzer 12.5. Debugging with the External Memory Interface Debug Toolkit 12.6. Generating Traffic with the Test Engine IP 12.7. Guidelines for Developing HDL for Traffic Generator 12.8. Guidelines for Traffic Generator Status Check 12.9. Hardware Debugging Guidelines 12.10. Categorizing Hardware Issues
12.1. Interface Configuration Performance Issues x
12.1.1. Interface Configuration Bottleneck and Efficiency Issues
12.2. Functional Issue Evaluation x
12.2.1. Altera IP Memory Model 12.2.2. Vendor Memory Model 12.2.3. Transcript Window Messages
12.3. Timing Issue Characteristics x
12.3.1. Evaluating FPGA Timing Issues 12.3.2. Evaluating External Memory Interface Timing Issues
12.5. Debugging with the External Memory Interface Debug Toolkit x
12.5.1. Prerequisites for Using the EMIF Debug Toolkit 12.5.2. Configuring a Design to Use the Debug Toolkit 12.5.3. Launching the EMIF Debug Toolkit 12.5.4. Using the EMIF Debug Toolkit
12.5.2. Configuring a Design to Use the Debug Toolkit x
12.5.2.1. Generating a Design Example with the Debug Toolkit
12.5.4. Using the EMIF Debug Toolkit x
12.5.4.1. Running Re-Calibration 12.5.4.2. Running the Test Engine
12.8. Guidelines for Traffic Generator Status Check x
12.8.1. Status Check Using the Signal Tap Logic Analyzer 12.8.2. Exporting the Status Interface to the Top-Level Design
12.9. Hardware Debugging Guidelines x
12.9.1. Create a Simplified Design that Demonstrates the Same Issue 12.9.2. Measure Power Distribution Network 12.9.3. Measure Signal Integrity and Setup and Hold Margin 12.9.4. Vary Voltage 12.9.5. Operate at a Lower Speed 12.9.6. Determine Whether the Issue Exists in Previous Versions of Software 12.9.7. Determine Whether the Issue Exists in the Current Version of Software 12.9.8. Try A Different PCB 12.9.9. Try Other Configurations 12.9.10. Debugging Checklist
12.10. Categorizing Hardware Issues x
12.10.1. Signal Integrity Issues 12.10.2. Hardware and Calibration Issues
12.10.1. Signal Integrity Issues x
12.10.1.1. Characteristics of Signal Integrity Issues 12.10.1.2. Evaluating Signal Integrity Issues 12.10.1.3. Skew 12.10.1.4. Crosstalk 12.10.1.5. Power System 12.10.1.6. Clock Signals 12.10.1.7. Address and Command Signals 12.10.1.8. Read Data Valid Window and Eye Diagram 12.10.1.9. Write Data Valid Window and Eye Diagram
12.10.2. Hardware and Calibration Issues x
12.10.2.1. Verifying High-Level Configuration 12.10.2.2. Verifying Memory Timing Parameters 12.10.2.3. Verifying the Correct Memory Component or DIMM Installed 12.10.2.4. Debugging Intermittent Issues
13. Agilex™ 5 FPGA EMIF IP - Mailbox Support x
13.1. Agilex™ 5 Mailbox Structure and Register Definitions 13.2. Accessing Read-Only Registers 13.3. Sending a Mailbox Command 13.4. IOSSM Mailbox Access Script
13.1. Agilex™ 5 Mailbox Structure and Register Definitions x
13.1.1. Mailbox Supported Commands 13.1.2. Mailbox Command Definitions 13.1.3. ECC Syndrome Codes 13.1.4. ECC Error Handling
13.2. Accessing Read-Only Registers x
13.2.1. Example 1: Reading IP_TYPE and IP_INSTANCE_ID of All the Interfaces in the IO96B Through Read-Only Registers 13.2.2. Example 2: Reading the Memory Clock Frequency for an Interface
13.3. Sending a Mailbox Command x
13.3.1. Example 3: Sending Recalibration Request and Reading Calibration Status Using the Mailbox
13.3.1. Example 3: Sending Recalibration Request and Reading Calibration Status Using the Mailbox x
13.3.1.1. Example 4: Sending ECC_INJECT_ERROR Using the Mailbox and Reading ECC Error Status, ECC Error Buffer Registers
13.4. IOSSM Mailbox Access Script x
13.4.1. Mailbox Script Overview 13.4.2. Running the Mailbox Script
13.4.1. Mailbox Script Overview x
13.4.1.1. mb_iossm_command.tcl 13.4.1.2. mb_user_input.tcl
1. About the External Memory Interfaces Agilex™ 5 FPGA IP
2. Agilex™ 5 FPGA EMIF IP – Introduction
3. Agilex™ 5 FPGA EMIF IP – Product Architecture
4. Agilex™ 5 FPGA EMIF IP – End-User Signals
5. Agilex™ 5 FPGA EMIF IP – Simulating Memory IP
6. Agilex™ 5 FPGA EMIF IP - DDR4 Support
7. Agilex™ 5 FPGA EMIF IP - DDR5 Support
8. Agilex™ 5 FPGA EMIF IP - LPDDR4 Support
9. Agilex™ 5 FPGA EMIF IP - LPDDR5 Support
10. Agilex™ 5 FPGA EMIF IP – Timing Closure
11. Agilex™ 5 FPGA EMIF IP – Controller Optimization
12. Agilex™ 5 FPGA EMIF IP – Debugging
13. Agilex™ 5 FPGA EMIF IP - Mailbox Support
14. Document Revision History for External Memory Interfaces (EMIF) IP User Guide

13.1.2. Mailbox Command Definitions

Table 238.  CMD_REQ Definition
Bit Name Description Access Reset
[31:29] CMD_TARGET_IP_TYPE Indicates the type of IP, as follows:
  • 0x0 – Not used.
  • 0x1 – Primary MC of primary IO96B.
  • 0x2 – Secondary MC of primary IO96B.
  • 0x3 – Primary MC of secondary IO96B.
  • 0x4 – Secondary MC of secondary IO96B.
 Read-Write 0x0
[28:24] CMD_TARGET_IP_INSTANCE_ID IP identifier. Read-Write 0x00
[23:16] CMD_TYPE The type of command that the user wants the firmware to perform. Read-Write 0x00
[15:0] CMD_OPCODE The opcode of the command that the user wants the firmware to perform. Read-Write 0x00
Table 239.  CMD_TYPE Definition
CMD_TYPE Value Description
CMD_NOP 0x00 No operation command.
CMD_TRIG_CONTROLLER_OP 0x04 Triggering memory controller-related operations.
CMD_TRIG_MEM_CAL_OP 0x05 Triggering calibration events.
Table 240.  CMD_TARGET_IP_TYPE Definition
Multi-channel/Lockstep Configurations CMD_TARGET_IP_TYPE
1 – Primary MC, Primary IO96B 2 – Secondary MC, Primary IO96B 3 – Primary MC, Secondary IO96B 4 – Secondary MC, Secondary IO96B
LPDDR4/5 2CHx16 CH1 CH2    
LPDDR4/5 4CHx16 CH1 CH2 CH3 CH4
DDR5 2CHx16 CH1 CH2    
DDR5 2CHx32 CH1   CH2  
DDR5 x40 lockstep CH1 *    
DDR4 x40 lockstep CH1 *    
DDR4 x64, x72 lockstep CH1 * * *
Note: * These controllers are used but have no (or limited) mailbox features due to limited lockstep capabilities.
Table 241.  Command Definitions
CMD_REQ Description

CMD_REQ [31:29]: CMD_TARGET_IP_TYPE = <TARGET_IP_TYPE>

CMD_REQ [28:24]: CMD_TARGET_IP_INSTANCE_ID = <TARGET_IP_INSTANCE_ID>

CMD_REQ [23:16]: CMD_TYPE = CMD_TRIG_CONTROLLER_OP

CMD_REQ [15:0]: CMD_OPCODE = ECC_ENABLE_SET

Command to enable different ECC modes for the memory interface specified using the instance ID. ECC mode can be changed only if the design was generated with ECC enabled.

[Inputs]

CMD_PARAM_0 [1:0]: ECC_ENABLE

Set the current ECC error reporting (single-bit and double-bit errors) and correcting (single-bit errors) that is enabled.

’b00 = ECC is disabled. Data is written to the memory without ECC values, and data is returned to the user interface without being verified for accuracy.

’b01 = ECC is enabled, but without detection or correction.

’b10 = ECC is enabled with detection, but correction is not supported. When an error is found on a read operation, ECC reporting parameters are updated for read commands. Erroneous data is returned to the user on read commands and written to the memory on write commands.

’b11 = ECC is enabled with detection and correction. When an error is found on a read operation, the ECC reporting parameters are updated for read commands. Single bit errors are corrected automatically by the controller in both read and write commands.

[Outputs]

[Errors]

CMD_RESPONSE_STATUS -

STATUS_CMD_RESPONSE_ERROR:

000 - No errors

001 - ECC was not enabled during design generation.

[Outputs] N/A

CMD_REQ [31:29]: CMD_TARGET_IP_TYPE = <TARGET_IP_TYPE>

CMD_REQ [28:24]: CMD_TARGET_IP_INSTANCE_ID = <TARGET_IP_INSTANCE_ID>

CMD_REQ [23:16]: CMD_TYPE = CMD_TRIG_CONTROLLER_OP

CMD_REQ [15:0]: CMD_OPCODE = ECC_INTERRUPT_MASK

Command to set mask for ECC interrupts for the memory interface specified using the instance ID, in order to disable specific ECC interrupts.

[Inputs]

CMD_PARAM_0 [13:0]: ECC_INTERRUPT_MASK

If any bit is set to ’b1 in this parameter, the corresponding interrupt does NOT trigger an interrupt on the top-level EMIF interrupt signal.

Bit [13] = A RMW Read Link ECC double-bit error has been detected

Bit [12] = A Read Link ECC double-bit error has been detected.

Bit [11] = A Read Link ECC single-bit error has been detected.

Bit [10] = A Write Link ECC double-bit error has been detected by the periodic MRR to MR43.

Bit [9] = A Write Link ECC single-bit error has been detected by the periodic MRR to MR43.

Bit [8] = An ECC correctable error has been detected in a scrubbing read operation

Bit [7] = The triggered scrub operation has completed.

Bit [6] = One or more ECC writeback commands could not be executed.

Bit [3] = Another un-correctable ECC event has been detected on a read operation, prior to the initial event being acknowledged.

Bit [2] = An un-correctable ECC event has been detected on a read operation.

Bit [1] = Another correctable ECC event has been detected on a read operation, prior to the initial event being acknowledged.

Bit [0] = A correctable ECC event has been detected on a read operation

[Outputs] N/A

CMD_REQ column is:

CMD_REQ [31:29]: CMD_TARGET_IP_TYPE = <TARGET_IP_TYPE>

CMD_REQ [28:24]: CMD_TARGET_IP_INSTANCE_ID = <TARGET_IP_INSTANCE_ID>

CMD_REQ [23:16]: CMD_TYPE = CMD_TRIG_CONTROLLER_OP

CMD_REQ [15:0]: CMD_OPCODE = ECC_WRITEBACK_ENABLE

Command to set automatic writing of corrected errors on read operation for the memory interface specified using the instance ID

CMD_PARAM_0 [0:0]: ECC_WRITEBACK_EN

Enables automatic writing of corrected data on single bit correctable errors on read operations. This parameter is only relevant if ECC is enabled with detection and correction (ECC_ENABLE = ’b11). Note: No writebacks will be issued during BIST. ’b0 = Disable. ’b1 = Enable

[Outputs] N/A

[Command-Specific Errors]

‘b000 – No errors

‘b001 – ECC detection and correction not enabled

CMD_REQ [31:29]: CMD_TARGET_IP_TYPE = <TARGET_IP_TYPE>

CMD_REQ [28:24]: CMD_TARGET_IP_INSTANCE_ID = <TARGET_IP_INSTANCE_ID>

CMD_REQ [23:16]: CMD_TYPE = CMD_TRIG_CONTROLLER_OP

CMD_REQ [15:0]: CMD_OPCODE = ECC_SCRUB_MODE_0_START

Command to start ECC scrub in mode 0 where scrub is performed at regular intervals for the memory interface specified using the instance ID. Automatic writing of corrected data should be enabled using the ECC_WRITEBACK_EN command before initiating scrub operations.

[Inputs]

CMD_PARAM_0 [15:0]: ECC_SCRUB_INTERVAL

Sets the minimum interval between two ECC scrubbing commands, in number of controller clock cycles. The controller clock is based on the Controller’s operating frequency. Clearing this parameter to 0x0000 disables interval operation.

CMD_PARAM_1 [11:0]: ECC_SCRUB_LEN

Defines the length (in bytes) of the ECC scrubbing read command that the controller issues. This value must be an integer multiple of the memory burst length, and the lowest 3 bits of this parameter must be cleared to ’b0. The burst lengths for different protocols are:

DDR4 - 8

DDR5/LPDDR4/LPDDR5 - 16

CMD_PARAM_2 [0:0]: ECC_SCRUB_FULL_MEM

Defines whether to perform ECC scrub on full memory or on the specified address range.

‘b0 – ECC scrub performed on address range specified using ECC_SCRUB_START_ADDR and ECC_SCRUB_END_ADDR

‘b1 – ECC scrub performed on full memory address range

CMD_PARAM_3 [31:0]: ECC_SCRUB_START_ADDR [31:0]

CMD_PARAM_4 [5:0]: ECC_SCRUB_START_ADDR [36:32]

Defines the starting address from where scrubbing operations begin. This value must be less than or equal to the value programmed into the ECC_SCRUB_END_ADDR parameter. Only used when ECC_SCRUB_FULL_MEM is ‘b0.

CMD_PARAM_5 [31:0]: ECC_SCRUB_END_ADDR [31:0]

CMD_PARAM_6 [5:0]: ECC_SCRUB_END_ADDR [36:32]

Defines the ending address at which scrubbing operations wrap around to the start address. This parameter must be programmed to a non-zero value for the scrubbing logic to operate. Only used when ECC_SCRUB_FULL_MEM is ‘b0.

[Outputs]

CMD_RESPONSE_DATA_SHORT [0:0]: ECC_SCRUB_INITIATED

‘b1 – ECC scrub initiated successfully

‘b0 – ECC scrub initiation failed

[Command-Specific Errors]

‘b000 – No errors

‘b001 – ECC not enabled

CMD_REQ [31:29]: CMD_TARGET_IP_TYPE = <TARGET_IP_TYPE>

CMD_REQ [28:24]: CMD_TARGET_IP_INSTANCE_ID = <TARGET_IP_INSTANCE_ID>

CMD_REQ [23:16]: CMD_TYPE = CMD_TRIG_CONTROLLER_OP

CMD_REQ [15:0]: CMD_OPCODE = ECC_SCRUB_MODE_1_START

Command to start ECC scrub in mode 1 where scrub is performed when the controller is idle for the memory interface specified using the instance ID. Automatic writing of corrected data should be enabled using the ECC_WRITEBACK_EN command before initiating scrub operations.

[Inputs]

CMD_PARAM_0 [15:0]: ECC_SCRUB_IDLE_CNT

Defines the number of controller clock cycles that the scrubbing engine waits in the Controller’s idle state before starting scrubbing operations. The Controller is considered idle when the command queue is empty. When this condition is detected, an internal counter loads with the value programmed in this parameter and count down on each controller clock. When the counter expires, either the scrubbing operation begins or the next address is tested. The controller clock is based on the Controller’s operating frequency. Clearing this parameter to 0x0000 disables idle operation.

CMD_PARAM_1 [11:0]: ECC_SCRUB_LEN

Defines the length (in bytes) of the ECC scrubbing read command that the controller issues. This value must be an integer multiple of the memory burst length, and the lowest 3 bits of this parameter must be cleared to ’b0. The burst lengths for different protocols are:

DDR4 - 8

DDR5/LPDDR4/LPDDR5 - 16

CMD_PARAM_2 [0:0]: ECC_SCRUB_FULL_MEM

Defines whether to perform ECC scrub on full memory or on the specified address range.

‘b0 – ECC scrub performed on address range specified using ECC_SCRUB_START_ADDR and ECC_SCRUB_END_ADDR

‘b1 – ECC scrub performed on full memory address range

CMD_PARAM_3 [31:0]: ECC_SCRUB_START_ADDR [31:0]

CMD_PARAM_4 [5:0]: ECC_SCRUB_START_ADDR [36:32]

Defines the starting address from where scrubbing operations begin. This value must be less than or equal to the value

programmed into the ECC_SCRUB_END_ADDR parameter. Only used when ECC_SCRUB_FULL_MEM is ‘b0.

CMD_PARAM_5 [31:0]: ECC_SCRUB_END_ADDR [31:0]

CMD_PARAM_6 [5:0]: ECC_SCRUB_END_ADDR [36:32]

Defines the ending address at which scrubbing operations wrap around to the start address. This parameter must be programmed to a non-zero value for the scrubbing logic to operate. Only used when ECC_SCRUB_FULL_MEM is ‘b0.

[Outputs]

CMD_RESPONSE_DATA_SHORT [0:0]: ECC_SCRUB_INITIATED

‘b1 – ECC scrub initiated successfully

‘b0 – ECC scrub initiation failed

[Command-Specific Errors]

‘b000 – No errors

‘b001 – ECC not enabled

CMD_REQ [31:29]: CMD_TARGET_IP_TYPE = <TARGET_IP_TYPE>

CMD_REQ [28:24]: CMD_TARGET_IP_INSTANCE_ID = <TARGET_IP_INSTANCE_ID>

CMD_REQ [23:16]: CMD_TYPE = CMD_TRIG_CONTROLLER_OP

CMD_REQ [15:0]: CMD_OPCODE = ECC_INJECT_ERROR

Command to force a specific check code to be written into memory interface specified using the instance ID for diagnostic purposes or for flagging a particular memory address as erroneous for future accesses. The procedure is as follows:

  1. Set the ECC_ENABLE parameter to enable detection (’b1x).
  2. Ensure that no writes to the controller are pending.
  3. Send ECC_INJECT_ERROR command through mailbox setting the ECC_XOR_CHECK_BITS input parameter. Use the syndromes to program the ECC_XOR_CHECK_BITS parameter. Each byte of the ECC_XOR_CHECK_BITS parameter controls the ECC event forcing for a separate user-word space. For example, setting a value of 0xF4 as ECC_XOR_CHECK_BITS will result in the check bits to be updated and written to the memory such that it flags a single-bit correctable error on bit [0] of the user-word on subsequent access of the same address.
  4. Execute a write command for an aligned user word. The controller will XOR the ECC_XOR_CHECK_BITS parameter with the generated checksum bits from the word written to the memory. The next read command to the same address will force the ECC error.
  5. Depending on the programming of the ECC_XOR_CHECK_BITS parameter, a single bit, double bit or multi-bit ECC error will occur. For single bit and double bit errors, the appropriate bit in the ECC_INTERRUPT_STATUS parameter will be set to ’b1 and the ECC error signature parameters will be filled with the relevant information.

[Inputs]

CMD_PARAM_0 [31:0]: ECC_XOR_CHECK_BITS

The check bits generated by the next write operation will be XOR’ed with this parameter. The result will be written into memory as the new check value.

ECC_XOR_CHECK_BITS [31:24] maps to user word [255:192]

ECC_XOR_CHECK_BITS [23:16] maps to user word [191:128]

ECC_XOR_CHECK_BITS [15:8] maps to user word [127:64]

ECC_XOR_CHECK_BITS [7:0] maps to user word [63:0]

[Outputs] N/A

[Command-Specific Errors]

‘b000 – No errors

‘b001 – ECC detection not enabled

CMD_REQ [31:29]: CMD_TARGET_IP_TYPE = <UNUSED>

CMD_REQ [28:24]: CMD_TARGET_IP_INSTANCE_ID = <UNUSED>

CMD_REQ [23:16]: CMD_TYPE = CMD_TRIG_CONTROLLER_OP

CMD_REQ [15:0]: CMD_OPCODE = ECC_CLEAR_ERR_BUFFER

Command to clear the ECC error buffer and reset the ECC error counter and overflow registers.

[Inputs] N/A

[Outputs] N/A

CMD_REQ [31:29]: CMD_TARGET_IP_TYPE = <TARGET_IP_TYPE>

CMD_REQ [28:24]: CMD_TARGET_IP_INSTANCE_ID = <TARGET_IP_INSTANCE_ID>

CMD_REQ [23:16]: CMD_TYPE = CMD_TRIG_CONTROLLER_OP

CMD_REQ [15:0]: CMD_OPCODE = BIST_STANDARD_MODE_START

Command to initiate Original MOVI1 3N BIST algorithm for data checking for the memory interface specified using the instance ID. Use BIST_STATUS_INTF0/ BIST_STATUS_INTF1 registers to get the status of the operation. BIST operations are supported only for designs with DBI disabled.

[Inputs]

CMD_PARAM_0 [5:0]: BIST_ADDR_SPACE [5:0]

Used in BIST data checking to define the address space in bytes from 0 to 2addr_space that the BIST logic will check. As an example, if the addr_space parameter was programmed to 0x1c, then the BIST logic would check 228 bytes = 256 MBytes. Only used if BIST_FULL_MEM is ‘b0.

A BIST test must cover a minimum of 2 bursts. Therefore, the user must program this parameter to a value such that the start address and end address of the BIST test will encompass a minimum of 2 bursts. The burst length for different protocols are:

DDR4 - 8

DDR5/LPDDR4/LPDDR5 – 16

CMD_PARAM_0 [6:6]: BIST_FULL_MEM

Defines whether to perform BIST on full memory or on the specified address range.

‘b0 – BIST performed on address range specified using BIST_START_ADDR and BIST_ADDR_SPACE

‘b1 – BIST performed on full memory address range

CMD_PARAM_1 [31:0]: BIST_START_ADDR [31:0]

CMD_PARAM_2 [5:0]: BIST_START_ADDR [36:32]

Used in BIST data checking and memory initialization programming to define the starting address for BIST checking in bytes. Only used if BIST_FULL_MEM is ‘b0.

[Outputs]

CMD_RESPONSE_DATA_SHORT [0:0]: BIST_INITIATED

‘b1 – BIST initiated successfully

‘b0 – BIST initiation failed

[Command-Specific Errors]

‘b00 – No errors

‘b01 – A previous command’s saved state not restored.

CMD_REQ [31:29]: CMD_TARGET_IP_TYPE = <TARGET_IP_TYPE>

CMD_REQ [28:24]: CMD_TARGET_IP_INSTANCE_ID = <TARGET_IP_INSTANCE_ID>

CMD_REQ [23:16]: CMD_TYPE = CMD_TRIG_CONTROLLER_OP

CMD_REQ [15:0]: CMD_OPCODE = BIST_MEM_INIT_START

Command to initiate memory initialization BIST for the memory interface specified using the instance ID. Memory initialization programming allows a selectable range of memory to be initialized with a programmable data value. Use MEM_INIT_STATUS_INTF0/ MEM_INIT_STATUS_INTF1 registers to get the status of the operation. If in-line ECC is enabled and you want to complete memory initialization on the entire memory, then before running the test, you should disable in-line ECC.

[Inputs]

CMD_PARAM_0 [5:0]: BIST_ADDR_SPACE [5:0]

Used in BIST data checking to define the address space in bytes from 0 to 2addr_space that the BIST logic will check. As an example, if the addr_space parameter was programmed to 0x1c, then the BIST logic would check 228 bytes = 256 MBytes. Only used if BIST_FULL_MEM is ‘b0.

Note: A BIST test must cover a minimum of 2 bursts. Therefore, the user must program this parameter to a value such that the start address and end address of the BIST test will encompass a minimum of 2 bursts. The burst length for different protocols are:

DDR4 - 8

DDR5/LPDDR4/LPDDR5 - 16

CMD_PARAM_0 [6:6]: BIST_FULL_MEM

Defines whether to perform BIST on full memory or on the specified address range.

‘b0 – BIST performed on address range specified using BIST_START_ADDR and BIST_ADDR_SPACE

‘b1 – BIST performed on full memory address range

CMD_PARAM_1 [31:0]: BIST_START_ADDR [31:0]

CMD_PARAM_2 [5:0]: BIST_START_ADDR [37:32]

Used in BIST data checking and memory initialization programming to define the starting address for BIST checking in bytes. Only used if BIST_FULL_MEM is ‘b0.

CMD_PARAM_3: BIST_DATA_PATTERN

Specifies the data pattern to use for the memory initialization.

‘b00 – Initialize memory to all zeros.

‘b10 – Use data pattern specified using the values set using commands BIST_SET_DATA_PATTERN_UPPER and BIST_SET_DATA_PATTERN_LOWER before issuing BIST_MEM_INITIAL_START command.

[Outputs]

CMD_RESPONSE_DATA_SHORT [0:0]: BIST_INITIATED

‘b1 – BIST memory initialization initiated successfully

‘b0 – BIST memory initialization initiation failed

[Command-Specific Errors]

‘b00 – No errors

‘b01 – A previous command’s saved state not restored.

‘b10 – In-line ECC must be disabled before full memory initialization. Either disable in-line ECC or specify a valid address range to be initialized.

CMD_REQ [31:29]: CMD_TARGET_IP_TYPE = <TARGET_IP_TYPE>

CMD_REQ [28:24]: CMD_TARGET_IP_INSTANCE_ID = <TARGET_IP_INSTANCE_ID>

CMD_REQ [23:16]: CMD_TYPE = CMD_TRIG_CONTROLLER_OP

CMD_REQ [15:0]: CMD_OPCODE = BIST_SET_DATA_PATTERN_UPPER

CMD_PARAM_3 [31:0]: BIST_DATA_PATTERN [287:256]

CMD_PARAM_2 [31:0]: BIST_DATA_PATTERN [255:224]

CMD_PARAM_1 [31:0]: BIST_DATA_PATTERN [223:192]

CMD_PARAM_0 [31:0]: BIST_DATA_PATTERN [191:160]

Defines the data pattern bits [287:160] to be used. Only data corresponding to active portion of core word is used while the inactive portion is ignored.

The active portion of the core word depends on the DQ width per channel and the burst length. For example:

- DDR5/LPDDR4/LPDDR5 (BL16) will use BIST_DATA_PATTERN [255:0] for x32 and BIST_DATA_PATTERN [127:0] for x16.

- DDR4 (BL8) will use BIST_DATA_PATTERN [127:0] for x32 and BIST_DATA_PATTERN [63:0] for x16.

If the axi4_rdata bus width is greater than the width of the active BIST_DATA_PATTERN, you will get repeated BIST_DATA_PATTERN when reading from the initialized memory locations. For example:

- DDR4 x32: axi4_rdata[255:0] = { 2{BIST_DATA_PATTERN[127:0] } }

- DDR4 x16: axi4_rdata[255:0] = { 4{BIST_DATA_PATTERN[63:0] } }

[Outputs] N/A

[Command-Specific Errors]

‘b00 – No errors

‘b01 – Cannot set upper data pattern for slim interface.

CMD_REQ [31:29]: CMD_TARGET_IP_TYPE = <TARGET_IP_TYPE>

CMD_REQ [28:24]: CMD_TARGET_IP_INSTANCE_ID = <TARGET_IP_INSTANCE_ID>

CMD_REQ [23:16]: CMD_TYPE = CMD_TRIG_CONTROLLER_OP

CMD_REQ [15:0]: CMD_OPCODE = BIST_SET_DATA_PATTERN_LOWER

CMD_PARAM_4 [31:0]: BIST_DATA_PATTERN [159:128]

CMD_PARAM_3 [31:0]: BIST_DATA_PATTERN [127:96]

CMD_PARAM_2 [31:0]: BIST_DATA_PATTERN [95:64]

CMD_PARAM_1 [31:0]: BIST_DATA_PATTERN [63:32]

CMD_PARAM_0 [31:0]: BIST_DATA_PATTERN [31:0]

Defines the data pattern bits [223:0] to be used. Only data corresponding to active portion of the core word is used while inactive portion is ignored.

The active portion of the core word depends on the DQ width per channel and the burst length. For example:

- DDR5/LPDDR4/LPDDR5 (BL16) will use BIST_DATA_PATTERN [255:0] for x32 and BIST_DATA_PATTERN [127:0] for x16.

- DDR4 (BL8) will use BIST_DATA_PATTERN [127:0] for x32 and BIST_DATA_PATTERN [63:0] for x16.

If the axi4_rdata bus width is greater than the width of the active BIST_DATA_PATTERN, you will get repeated BIST_DATA_PATTERN when reading from the initialized memory locations. For example:

- DDR4 x32: axi4_rdata[255:0] = { 2{BIST_DATA_PATTERN[127:0] } }

- DDR4 x16: axi4_rdata[255:0] = { 4{BIST_DATA_PATTERN[63:0] } }

CMD_REQ [31:29]: CMD_TARGET_IP_TYPE = <TARGET_IP_TYPE>

CMD_REQ [28:24]: CMD_TARGET_IP_INSTANCE_ID = <TARGET_IP_INSTANCE_ID>

CMD_REQ [23:16]: CMD_TYPE = CMD_TRIG_CONTROLLER_OP

CMD_REQ [15:0]: CMD_OPCODE = CHANGE_FSP_LP5

Command to change the FSP when using the LPDDR5 protocol.

[Inputs]

CMD_PARAM_0 [1:0]:

TARGET_FSP

‘b00 – FSP 0

‘b01 – FSP 1

‘b10 – FSP 2

[Outputs]

CMD_RESPONSE_DATA_SHORT [0:0]:

FSP_CHANGE_STATUS

‘b1 – The FSP was changed successfully.

‘b0 – The FSP was not changed successfully.

[Error Codes]

‘b000 – No errors.

‘b001 – Current Protocol is not LPDDR5.

‘b010 – The current FSP is equal to the target FSP – No change is needed.

‘b011 – The FSP could not be changed.

CMD_REQ [31:29]: CMD_TARGET_IP_TYPE = <TARGET_IP_TYPE>

CMD_REQ [28:24]: CMD_TARGET_IP_INSTANCE_ID = <TARGET_IP_INSTANCE_ID>

CMD_REQ [23:16]: CMD_TYPE = CMD_TRIG_CONTROLLER_OP

CMD_REQ [15:0]: CMD_OPCODE = LP_MODE_ENTER

Command to cause the Interface to enter a low power state. Note that other interface operations, including recalibration and mode register reads and writes, can cause automatic exits from some low-power states.

[Inputs]

CMD_PARAM_0[3:0]: LP_STATE

Specified the low power state the interface should enter:

‘b1000 – Self-Refresh Long (DDR4/DDR5 Only)

‘b1001 – Self-Refresh Long with Memory Clock Gating (DDR4/DDR5 Only)

‘b1010 – Self-Refresh Long with Memory Clock and Controller Clock Gating (DDR4/DDR5 Only)

‘b1101 – Self-Refresh Power Down Long (LPDDR4/LPDDR5 Only)

‘b1110 – Self-Refresh Power Down Long with Memory Clock Gating (LPDDR4/LPDDR5 Only)

‘b1111 – Self-Refresh Power Down Long with Memory and Controller Clock Gating (LPDDR4/LPDDR5 Only)

[Outputs] N/A

[Error Codes]

‘b000 – No errors

‘b001 – The Selected Low Power State is Not Available for the Current Protocol

‘b010 – The Selected Low Power State is invalid/Does not Exist.

‘b011 – Disable auto LP mode using the LP_MODE_AUTO command and confirm the idle state using the LP_MODE_STATUS command before using the LP_MODE_ENTER command.

CMD_REQ [31:29]: CMD_TARGET_IP_TYPE = <TARGET_IP_TYPE>

CMD_REQ [28:24]: CMD_TARGET_IP_INSTANCE_ID = <TARGET_IP_INSTANCE_ID>

CMD_REQ [23:16]: CMD_TYPE = CMD_TRIG_CONTROLLER_OP

CMD_REQ [15:0]: CMD_OPCODE = LP_MODE_EXIT

Command to exit any low power state.

[Inputs] N/A

[Outputs] N/A

[Error Codes]

‘b000 – No errors

CMD_REQ [31:29]: CMD_TARGET_IP_TYPE = <TARGET_IP_TYPE>

CMD_REQ [28:24]: CMD_TARGET_IP_INSTANCE_ID = <TARGET_IP_INSTANCE_ID>

CMD_REQ [23:16]: CMD_TYPE = CMD_TRIG_CONTROLLER_OP

CMD_REQ [15:0]: CMD_OPCODE = LP_MODE_AUTO

Command to cause the Interface to enter certain automatic low power states. Supported low power modes for this command are listed below as valid options. Do not use LP_MODE_EXIT opcode to exit from the automatic low power states. Note that other interface operations, including recalibration and mode register reads and writes, sending read/write request to the controller can cause automatic exits from some low-power states.

[Inputs]

CMD_PARAM_0 [3:0]:

Specified the low power state the interface should enter.

‘b0000 – Disable automatic low power mode.

‘b0001 – Active Power Down (All Protocols).

‘b0010 – Active Power Down with Memory Clock Gating (LPDDR4/LPDDR5 only).

‘b0011 – Pre-Charge Power Down (All Protocols).

‘b0100 – Pre-Charge Power Down with Memory Clock Gating (LPDDR4/LPDDR5 only).

‘b0101 – Self-Refresh Short (DDR4/DDR5 only).

‘b0110 – Self-Refresh Short with Memory Clock Gating (DDR4/DDR5 only).

‘b1011 – Self-Refresh Power Down Short (LPDDR4/LPDDR5 only).

‘b1100 – Self-Refresh Power Down Short with Memory Clock Gating (LPDDR4/LPDDR5 only).

CMD_PARAM_1 [11:0]:

Defines the number of idle controller clocks that can elapse before the controller will automatically issue an entry into the low power state specified

[Outputs]

[Error Codes]

‘b000 – No errors

‘b001 – The selected low power state is invalid for the current protocol.

‘b010 – The selected low power state is invalid/does not exist.

‘b011 – The idle clock count should not be zero.

CMD_REQ [31:29]: CMD_TARGET_IP_TYPE = <TARGET_IP_TYPE>

CMD_REQ [28:24]: CMD_TARGET_IP_INSTANCE_ID = <TARGET_IP_INSTANCE_ID>

CMD_REQ [23:16]: CMD_TYPE = CMD_TRIG_MEM_CAL_OP

CMD_REQ [15:0]: CMD_OPCODE = TRIG_MEM_CAL

Command to trigger a memory calibration for the memory interface specified using the instance ID. You should only recalibrate the memory interface for debug purposes. (HPS EMIF on Agilex™ 5 devices does not support recalibration.)

For multi-channel interfaces, recalibration can be initiated by sending the TRIG_MEM_CAL command as below:

  • 1 channel – 1 request to the interface
  • 2 channel LPDDR4/LPDDR5 – 1 request to one of the interfaces
  • 2 channel DDR5 – 2 separate requests to the interfaces in each IO96B
  • 4 channel LPDDR4/LPDDR5 – 2 requests to one of the interfaces in each IO96B

[Inputs]

[Outputs]

CMD_RESPONSE_DATA_SHORT [0]: MEM_CAL_INITIATED

‘b1 – Memory calibration triggered successfully

‘b0 – Memory calibration triggering failed

[Errors]

CMD_RESPONSE_STATUS - STATUS_CMD_RESPONSE_ERROR:

000 - No errors

001 - Triggering memory calibration is not supported for this memory interface.
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