External Memory Interfaces (EMIF) IP User Guide: Agilex™ 5 FPGAs and SoCs

ID 817467
Date 3/31/2025
Public
Document Table of Contents

4.2.10. mem_0 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - DDR5 Component

Interface to the memory (channel 0), including all CA pins, DQ pins, and DQS pins.

Table 51.  Interface: mem_0Interface type: conduit
Port Name Direction Description
mem_0_cs_n Output Chip Select channel 0.
mem_0_ca Output Command/Address Bus channel 0.
mem_0_dq Bidir Data (read/write) channel 0.
mem_0_dqs_t Bidir Data Strobe (true) channel 0.
mem_0_dqs_c Bidir Data Strobe (complement) channel 0.
mem_0_alert_n Input Indicates Write CRC Error channel 0.