External Memory Interfaces (EMIF) IP User Guide: Agilex™ 5 FPGAs and SoCs

ID 817467
Date 3/31/2025
Public
Document Table of Contents

4.4.6. s1_axi4_clock_out for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR5

Output user clock for mainband (from CPA of secondary I/O bank); for MAINBAND_ACCESS_MODE = SYNC only.

Table 97.  Interface: s1_axi4_clock_outInterface type: clock
Port Name Direction Description
s1_axi4_clock_out Output User clock for maiband axi (secondary I/O bank). Output clock from the EMIF IP (output from CPA block, synchronous to PHY clock).