Intel Agilex® 7 LVDS SERDES User Guide: M-Series

ID 768615
Date 11/28/2023

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Document Table of Contents

3.2.1. Serializer Bypass for DDR and SDR Operations

The I/O element (IOE) contains two data output registers. Each data output register can operate in double data rate (DDR) or single data rate (SDR) mode. Use the GPIO Intel® FPGA IP to bypass the serializer and operate in DDR and SDR modes.
Figure 5. Serializer BypassThis figure shows the serializer bypass path.

Table 6.  SDR and DDR Transmitter Modes
Mode Description
SDR (×1)
  • The IOE data width is 1 bit.
  • Serialization factor of 1.
  • Registered output path requires a clock.
  • Data is passed directly through the IOE.
DDR (×2)
  • The IOE data width is 2 bits.
  • Serialization factor of 2.
  • The GPIO IP requires a clock.
  • tx_inclock clocks the IOE register.