Intel Agilex® 7 LVDS SERDES User Guide: M-Series

ID 768615
Date 11/28/2023

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4.1.3. Data Realignment Block (Bit Slip)

Skew in the transmitted data, along with skew added by the link, causes channel-to-channel skew on the received serial data streams. If you enable the DPA, the received data is captured with different clock phases on each channel. This difference may cause misalignment of the received data from channel to channel.

To compensate for the channel-to-channel skew and establish the correct received word boundary at each channel, each receiver channel has a dedicated data realignment circuit that realigns the data by inserting bit latencies into the serial stream.

The optional rx_bitslip_ctrl signal controls the bit insertion of each receiver that is independently controlled from the internal logic. The data slips one bit on the rising edge of rx_bitslip_ctrl.

The rx_bitslip_ctrl signal has the following requirements:

  • The minimum pulse width is one period of the parallel clock in the logic array.
  • The minimum low time between pulses is one period of the parallel clock.
  • The signal is an edge-triggered signal.
  • The valid data is available six parallel clock cycles after the rising edge of rx_bitslip_ctrl.

The MSB from the serial data is not the MSB of the parallel data. You can use the bit slip to set the proper word boundary on the parallel data.

Figure 9. Data Realignment TimingThis figure shows the receiver output (rx_out) signal after a 1-bit slip pulse with the deserialization factor of 4.

The bit slip rollover value of the data realignment circuit is set to the deserialization factor. An optional rx_bitslip_max status signal, available to the FPGA fabric from each channel, indicates arrival to the preset rollover point.

Figure 10. Receiver Data Realignment RolloverThis figure shows a preset value of 4-bit cycles before the rollover occurs. The rx_bitslip_max signal pulses for one coreclock cycle to indicate that rollover has occurred.