Intel Agilex® 7 LVDS SERDES User Guide: M-Series

ID 768615
Date 11/28/2023

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Document Table of Contents

2.1. Intel Agilex® 7 GPIO-B Banks, SERDES, and DPA Locations

The GPIO-B banks are located at the top and bottom I/O bank rows.
Figure 1.  M-Series I/O Bank Structure (Die Top View)This figure shows the GPIO-B bank structure of the M-Series device. The figure shows the view of the die as shown in the Intel® Quartus® Prime Chip Planner. In the Pin Planner, this corresponds to the "Bottom View". Different device packages have different number of GPIO-B banks. Refer to the device pin-out files for available GPIO-B banks and the locations of the SDM shared and HPS shared GPIO-B banks for each device package.