Intel Agilex® 7 LVDS SERDES User Guide: M-Series

ID 768615
Date 11/28/2023

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11. Document Revision History for the Intel Agilex® 7 LVDS SERDES User Guide: M-Series

Document Version Intel® Quartus® Prime Version Changes
2023.11.28 23.2 Added notes that serialization factor of 8 is available only for production devices.
2023.09.26 23.2 Added a link from the topic about planning the LVDS interface to a topic that shows the valid and invalid scenarios.
2023.08.08 23.2
  • Removed the note about restricted support of M-Series FPGAs.
  • Changed the term "high-speed SERDES" to "LVDS SERDES".
  • Updated the figure showing the I/O bank structure.
  • Changed tx_coreclock and rx_coreclock to coreclock.
  • Updated the topic about LVDS SERDES usage modes.
  • Updated the number of clock cycles before valid data is available after bit slip.
  • Added LVDS SERDES Intel FPGA IP information.
  • Updated the topics related to setting up LVDS interface with external PLL mode.
  • Updated guidelines for pin placement for differential channels.
  • Added topic about PLLs driving LVDS transmitter and receiver channels.
  • Added information about timing.
  • Added information about design examples.
  • Added troubleshooting guidelines.
  • Added topics related to planning your LVDS interface pins and selecting bytes and pins in the Pin Settings tab.
  • Added topic about placement restrictions if you mix true differential and single-ended I/O standards in the same or adjacent HSIO banks.
2023.04.03 Initial release.