6.1.3. Timing Analysis for the External PLL Mode
The Intel® Quartus® Prime software derives some of the SERDES constraints from the PLL clocks. Therefore, the Intel® Quartus® Prime software must generate the external PLL clock settings before the LVDS SERDES IP clock settings. In the .qsf of your project, ensure that the line for the .ip file of the IOPLL IP appears before the line for the .ip file of the LVDS SERDES IP.