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1. Intel Agilex® 7 M-Series LVDS SERDES Overview
2. Intel Agilex® 7 M-Series LVDS SERDES Architecture
3. Intel Agilex® 7 M-Series LVDS SERDES Transmitter
4. Intel Agilex® 7 M-Series LVDS SERDES Receiver
5. Intel Agilex® 7 M-Series High-Speed LVDS I/O Implementation Guide
6. Intel Agilex® 7 M-Series LVDS SERDES Timing
7. LVDS SERDES Intel® FPGA IP Design Examples
8. Intel Agilex® 7 M-Series LVDS SERDES Design Guidelines
9. Intel Agilex® 7 M-Series LVDS SERDES Troubleshooting Guidelines
10. Documentation Related to the Intel Agilex® 7 LVDS SERDES User Guide: M-Series
11. Document Revision History for the Intel Agilex® 7 LVDS SERDES User Guide: M-Series
8.1. Use PLLs in Integer PLL Mode for LVDS
8.2. Use High-Speed Clock from PLL to Clock SERDES Only
8.3. Pin Placement for Differential Channels
8.4. SERDES Pin Pairs for Soft-CDR Mode
8.5. Placing LVDS Transmitters and Receivers in the Same GPIO-B Sub-Bank
8.6. VCCIO_PIO Power Scheme for LVDS SERDES
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6. Intel Agilex® 7 M-Series LVDS SERDES Timing
The true differential I/O standard enables high-speed transmission of data, resulting in better overall system performance. To take advantage of fast system performance, you must analyze the timing for these high-speed signals. Timing analysis for the differential block is different from traditional synchronous timing analysis techniques.