Intel Agilex® 7 LVDS SERDES User Guide: M-Series

ID 768615
Date 11/28/2023

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

5.1.2. LVDS SERDES Intel® FPGA IP Features

The LVDS SERDES IP includes features for the LVDS receiver and transmitter. You can use the Intel® Quartus® Prime parameter editor to configure the LVDS SERDES IP.

The LVDS SERDES IP provides the following features for you to implement your LVDS I/O design:

  • Parameterizable data channel widths
  • Parameterizable SERDES factors
  • Registered input and output ports
  • PLL control signals
  • Non-DPA mode
  • DPA mode
  • Soft clock data recovery (CDR) mode