1. Intel Agilex® 7 M-Series LVDS SERDES Overview 2. Intel Agilex® 7 M-Series LVDS SERDES Architecture 3. Intel Agilex® 7 M-Series LVDS SERDES Transmitter 4. Intel Agilex® 7 M-Series LVDS SERDES Receiver 5. Intel Agilex® 7 M-Series High-Speed LVDS I/O Implementation Guide 6. Intel Agilex® 7 M-Series LVDS SERDES Timing 7. LVDS SERDES Intel® FPGA IP Design Examples 8. Intel Agilex® 7 M-Series LVDS SERDES Design Guidelines 9. Intel Agilex® 7 M-Series LVDS SERDES Troubleshooting Guidelines 10. Documentation Related to the Intel Agilex® 7 LVDS SERDES User Guide: M-Series 11. Document Revision History for the Intel Agilex® 7 LVDS SERDES User Guide: M-Series
8.1. Use PLLs in Integer PLL Mode for LVDS 8.2. Use High-Speed Clock from PLL to Clock SERDES Only 8.3. Pin Placement for Differential Channels 8.4. SERDES Pin Pairs for Soft-CDR Mode 8.5. Placing LVDS Transmitters and Receivers in the Same GPIO-B Sub-Bank 8.6. VCCIO_PIO Power Scheme for LVDS SERDES
8.3. Pin Placement for Differential Channels
Each M-Series GPIO-B sub-bank contains its own PLL. The PLL can drive all receiver and transmitter channels in the same bank. You must use the dedicated clock pins to drive the LVDS PLLs. Each bank supports driving two PLLs from the same bank with a single reference clock.
Pins Arrangement in the GPIO-B Bank
In the device pin out files, the following pin index numbers indicate the location of the pins in a single GPIO-B bank:
- 0 to 47—bottom index sub-bank
- 48 to 95—top index sub-bank
PLLs Driving DPA-Enabled Differential Channels
- For differential channels, the PLL can drive all channels in the same I/O bank but cannot drive channels in other banks.
- Each differential receiver in an I/O bank has a dedicated DPA circuit to align the phase of the clock to the data phase of its associated channel.
- DPA usage adds some constraints to the placement of high-speed differential receiver channels. The Intel® Quartus® Prime compiler automatically checks the design and issues error messages if there are placement guidelines violations. Adhere to the guidelines to ensure proper high-speed I/O operation.