Intel Agilex® 7 LVDS SERDES User Guide: M-Series

ID 768615
Date 11/28/2023

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Document Table of Contents

8.3. Pin Placement for Differential Channels

Each M-Series GPIO-B sub-bank contains its own PLL. The PLL can drive all receiver and transmitter channels in the same bank. You must use the dedicated clock pins to drive the LVDS PLLs. Each bank supports driving two PLLs from the same bank with a single reference clock.

Pins Arrangement in the GPIO-B Bank

In the device pin out files, the following pin index numbers indicate the location of the pins in a single GPIO-B bank:

  • 0 to 47bottom index sub-bank
  • 48 to 95top index sub-bank

PLLs Driving DPA-Enabled Differential Channels

  • For differential channels, the PLL can drive all channels in the same I/O bank but cannot drive channels in other banks.
  • Each differential receiver in an I/O bank has a dedicated DPA circuit to align the phase of the clock to the data phase of its associated channel.
  • DPA usage adds some constraints to the placement of high-speed differential receiver channels. The Intel® Quartus® Prime compiler automatically checks the design and issues error messages if there are placement guidelines violations. Adhere to the guidelines to ensure proper high-speed I/O operation.