Intel Agilex® 7 LVDS SERDES User Guide: M-Series

ID 768615
Date 11/28/2023
Public

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5.2.3. Connection between IOPLL IP and LVDS SERDES IP in External PLL Mode

Figure 25. Non-DPA or DPA LVDS Receiver Interface with the IOPLL IP without LVDS Transmitter in the Same Sub-Bank


Figure 26. Non-DPA or DPA LVDS Receiver Interface with the IOPLL IP with LVDS Transmitter in the Same Sub-Bank


Figure 27. Soft-CDR LVDS Receiver Interface with the IOPLL IP without LVDS Transmitter in the Same Sub-Bank


Figure 28. Soft-CDR LVDS Receiver Interface with the IOPLL IP with LVDS Transmitter in the Same Sub-Bank


Figure 29. LVDS Transmitter Interface with the IOPLL IP


In the external PLL mode, the LVDS SERDES IP automatically turns on the ext_pll_1_outclock2 port. If you do not connect the ext_pll_1_outclock2 port as shown in the preceding figures, the Intel® Quartus® Prime compiler outputs error messages.