4.1.1. Dynamic Phase Alignment Block
The DPA block selects a phase closest to the phase of the serial data. The maximum phase offset between the received data and the selected phase is unit interval (UI)5 , which is the maximum quantization error of the DPA. The eight phases of the clock divides equally, offering a 45° resolution.
The DPA block continuously monitors the phase of the incoming serial data and selects a new clock phase when required. To prevent the DPA from selecting a new clock phase, assert the optional rx_dpa_hold signal available for each channel.
The DPA circuitry does not require a fixed training pattern to lock to the optimum phase out of the eight phases. After reset or power up, the DPA circuitry requires transitions on the received data to lock to the optimum phase. The optional rx_dpa_locked output signal indicates an initial DPA lock condition to the optimum phase after power up or reset. To validate the data, use data checkers such as a cyclic redundancy check (CRC) or diagonal interleaved parity (DIP-4).
The independent rx_dpa_reset reset signal resets the DPA circuitry. After a reset, retrain the DPA circuitry.