1. Intel Agilex® 7 M-Series LVDS SERDES Overview 2. Intel Agilex® 7 M-Series LVDS SERDES Architecture 3. Intel Agilex® 7 M-Series LVDS SERDES Transmitter 4. Intel Agilex® 7 M-Series LVDS SERDES Receiver 5. Intel Agilex® 7 M-Series High-Speed LVDS I/O Implementation Guide 6. Intel Agilex® 7 M-Series LVDS SERDES Timing 7. LVDS SERDES Intel® FPGA IP Design Examples 8. Intel Agilex® 7 M-Series LVDS SERDES Design Guidelines 9. Intel Agilex® 7 M-Series LVDS SERDES Troubleshooting Guidelines 10. Documentation Related to the Intel Agilex® 7 LVDS SERDES User Guide: M-Series 11. Document Revision History for the Intel Agilex® 7 LVDS SERDES User Guide: M-Series
8.1. Use PLLs in Integer PLL Mode for LVDS 8.2. Use High-Speed Clock from PLL to Clock SERDES Only 8.3. Pin Placement for Differential Channels 8.4. SERDES Pin Pairs for Soft-CDR Mode 8.5. Placing LVDS Transmitters and Receivers in the Same GPIO-B Sub-Bank 8.6. VCCIO_PIO Power Scheme for LVDS SERDES
220.127.116.11.3. Locating the I/O Lane and Channel Pin through the Interface Planner
After you have assigned the channel byte to an I/O lane, you can refer to information in the Interface Planner to verify the I/O lane number and pin index numbers.
- Select the channel byte design element (already placed) under the Design section.
- Refer to the Device Location > resources field in the Info tab under the Info section.
The number in the byte resource corresponds to the I/O lane number shown in the Pin Planner. For example, if the resource is BYTE-3, this corresponds to I/O Lane 3.
- To determine the I/O pins of the LVDS channels and the respective I/O bank:
- Clear the Design Element Filter box under the Design section.
- Switch to the Link Info tab.
- Click the hyperlink for the channel in the Fanin > IO_CLUSTER category.
For example, to verify the pins for receiver channel 0, click rx_in_p~CLUSTER.The list under the Design section selects the design channel design element.
- Clear the Filter box under the Legal Locations section.
- Right-click the selected design element row and select Generate Legal Locations for Selected Element.
The Legal Locations section displays the differential pin pair.
- Right-click the differential pin pair in the Legal Locations section and select Zoom to Selected.
The chip view zooms to the pin pair and highlight them.
- Hover your mouse cursor at the edge of the selected I/O pad to view the bank and pin names.
- Click at the edge of the selected I/O pad to display the resource property under the Info section.
The Device Location > resources category displays the pad number that corresponds to the pin index number as shown in the Pin Planner and pin out files.
Figure 23. Interface Planner Showing the Bank Name, Pin Name, and Pin Index Number
You can compare how the assigned pins correspond to your channel selection in the Pin Settings tab of the LVDS SERDES IP parameter editor. For example, if you selected pin pair "0203" as the channel for byte 0, and then placed byte 0 to I/O lane 3 of bank 3A_B, the pins assigned to the channel has the index numbers as listed in Table 15.