Intel Agilex® 7 LVDS SERDES User Guide: M-Series

ID 768615
Date 11/28/2023

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4.1. LVDS SERDES Receiver Blocks

The True Differential Signaling and SLVS-400 buffers can interface with LVDS, mini-LVDS, RSDS, and LVPECL compatible signaling. You can statically set the I/O standard of the receiver pins to True Differential Signaling in the Intel® Quartus® Prime Assignment Editor or .qsf file.
Figure 7. Receiver Block DiagramThis figure shows the hardware blocks of the receiver. In SDR and DDR modes, the data width from the IOE is 1 and 2 bits, respectively. The deserializer includes shift registers and parallel load registers, and sends a maximum of 8 bits to the internal logic.

Note: The PLL that drives the SERDES channel must operate in integer PLL mode. You do not need a PLL if you bypass the deserializer