Intel Agilex® 7 LVDS SERDES User Guide: M-Series

ID 768615
Date 11/28/2023

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5.1.4. Planning the LVDS Interface

In Intel Agilex® 7 devices, you must plan your LVDS interface before setting up the LVDS SERDES IP, especially the placement of the pins.

The purpose of the following steps is to identify the location of the pin using the Intel® Quartus® Prime Pin Planner and Chip Planner tools. Knowing the location of the pins helps you place the LVDS channel bytes in I/O lanes using the Intel® Quartus® Prime Interface Planner tool.

  1. Plan the interface width, the combination of receiver and transmitter channels, and where to place the pins.
    • An LVDS interface can span across sub-banks but must be within the same GPIO-B bank. Refer to the related information for valid and invalid scenarios.
    • The channels of the LVDS interface can be any differential pin pair combinations within the bank and do not need to be sequential.
    • In each GPIO-B bank, reserve a pair of pins for the reference clock.
    • Refer to the related information about the placement restrictions for differential pins. The placement restrictions guidelines list the pins using the pin index numbers within the I/O bank.
  2. Based on the GPIO-B bank and pin index numbers you plan to use, refer to the device pin out file to determine the pin names.
    Note: The following steps are optional but recommended. If you are familiar with the device layout, you can use the Intel® Quartus® Prime Interface Planner to find the pin location and subsequently the respective I/O lane. You need to run Analysis & Synthesis before you can use the Interface Planner. Refer to GPIO-B Pin Index Number and Respective Channel Pin Selection to determine which pin channel to select based on the pin index number and I/O lane you plan to use.
  3. In the Intel® Quartus® Prime Pin Planner tool, under the Tasks window, double-click Highlight Pins > I/O 12 Lanes.
    The Pin Planner highlights and color-codes the pins according to the I/O lanes.
  4. Using the pin name, locate the pin you want and take note of the I/O lane.

    You need these information later to select the channel pin when setting up the LVDS SERDES IP parameters.

    Figure 18. Pin Planner Showing the Pins According to I/O Lanes

  5. Right-click the pin, and select Locate Node > Locate in Chip Planner.
    The Chip Planner displays the full name and coordinate of the pin.
  6. Take note of the full name of the pin.
    You need this information later to identify the I/O lane where you want to place the channel byte you select in the Pin Settings tab in the LVDS SERDES IP parameter editor.
    Figure 19. Chip Planner Showing the Pin Full Name and Coordinate

  7. Repeat from step 4 for one pin in each I/O lane.
    You only need to locate one pin from each I/O lane.
After completing the procedure, you have a list of pins you want to use and the coordinate of at least one pin in each I/O lane. The pin coordinate helps you to identify its I/O lane in the Intel® Quartus® Prime Interface Planner.

The next steps are:

  • Configure and generate your LVDS SERDES IP.
  • Instantiate the LVDS SERDES IP in your design.
  • Run Analysis & Synthesis on your project.
  • Use the Intel® Quartus® Prime Interface Planner to place your LVDS channel bytes in I/O lanes.