3.3. Clocking the Differential Transmitters
You can configure any M-Series transmitter data channel to generate a source-synchronous transmitter clock output. This allows placement of the output clock near the data outputs to simplify board layout and reduce clock-to-data skew.
Different applications often require specific clock-to-data alignments or specific data-rate-to-clock-rate factors. You can specify these settings statically in the LVDS SERDES Intel® FPGA IP parameter editor:
- The transmitter can output a clock signal at the same rate as the data with a maximum output clock frequency supported by the device speed grade.
- You can divide the output clock by a factor of 4 or 8, depending on the serialization factor.
- You can set the phase of the clock in relation to the data at 0° (edge-aligned) or 180° (center-aligned). The I/O PLLs provide additional support for other phase shifts in 45° increments.