Intel Agilex® 7 LVDS SERDES User Guide: M-Series

ID 768615
Date 11/28/2023

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Document Table of Contents

5.2.1. IOPLL IP Signal Interface with LVDS SERDES IP

Table 25.  Signal Interface between IOPLL and LVDS SERDES IPs This table lists the signal interface between the output ports of the IOPLL IP and the input ports of the LVDS SERDES IP transmitter or receiver.
From the IOPLL IP To the LVDS SERDES IP Transmitter or Receiver
outclock_periph[1:0] (serial clock output signal)
  • Configure this signal using outclk0 in the PLL.
  • Turn on Enable access to I/O Bank clock ports option under the LVDS External PLL section.

The serial clock output can only drive ext_outclock_periph[1:0] on the LVDS SERDES IP transmitter and receiver. This clock cannot drive the core logic.

ext_outclock_periph[1:0] (serial clock input to the transmitter or receiver)

outclk_2 (parallel clock output)

ext_pll_1_outclock2 (core clock to the LVDS SERDES Intel FPGA IP)



This signal indicates when external PLL is locked. It does not indicate if SERDES is ready for initialization.


pll_areset (asynchronous PLL reset port)


  • This signal is required if ext_vcoph[7:0] is required.

  • Configure this signal by turning on Specify VCO frequency in the PLL and specifying the Desired VCO Frequency value.
  • Turn on Enable access to PLL DPA output port.


This signal is required for all transmitter or receiver modes.