Intel Agilex® 7 LVDS SERDES User Guide: M-Series

ID 768615
Date 11/28/2023

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4. Intel Agilex® 7 M-Series LVDS SERDES Receiver

The M-Series LVDS SERDES receivers are dedicated circuitries.
Dedicated Circuitry and Features of the LVDS SERDES Receiver
Dedicated Circuitry / Feature Description
Differential I/O buffer

Supports I/O standards compatible with LVDS, RSDS, SLVS, Mini-LVDS, and LVPECL:

  • DPA mode—True Differential Signaling and SLVS-400 I/O standards
  • Non-DPA mode—True Differential Signaling I/O standard only
Deserializer Up to 4-bit or 8-bit wide deserializer
Phase-locked loops (PLLs) Generates different phases of a clock for data synchronizer
Data realignment (bit slip) Inserts bit latencies into serial data
Dynamic phase alignment (DPA) Chooses a phase closest to the phase of the serial data
Synchronizer (FIFO buffer) Compensate for phase differences between the data and the receiver’s input reference clock
On-chip termination (OCT) RD 100 Ω in True Differential Signaling I/O standards