Intel Agilex® 7 LVDS SERDES User Guide: M-Series

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ID 768615
Date 4/03/2023
Public

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Document Table of Contents
Document Table of Contents x
1. Intel Agilex® 7 M-Series LVDS SERDES Overview 2. Intel Agilex® 7 M-Series High-Speed SERDES Architecture 3. Intel Agilex® 7 M-Series LVDS SERDES Transmitter 4. Intel Agilex® 7 M-Series LVDS SERDES Receiver 5. Intel Agilex® 7 M-Series High-Speed SERDES Design Guidelines 6. Documentation Related to the Intel Agilex® 7 LVDS SERDES User Guide: M-Series 7. Document Revision History for the Intel Agilex® 7 LVDS SERDES User Guide: M-Series
2. Intel Agilex® 7 M-Series High-Speed SERDES Architecture x
2.1. Intel Agilex® 7 GPIO-B Banks, SERDES, and DPA Locations 2.2. SERDES Blocks, Modes, and Clock Domains
3. Intel Agilex® 7 M-Series LVDS SERDES Transmitter x
3.1. LVDS SERDES Transmitter Blocks 3.2. Serializer 3.3. Clocking the Differential Transmitters
3.2. Serializer x
3.2.1. Serializer Bypass for DDR and SDR Operations 3.2.2. Differential I/O Bit Position
4. Intel Agilex® 7 M-Series LVDS SERDES Receiver x
4.1. LVDS SERDES Receiver Blocks 4.2. Clocking the LVDS SERDES Receivers 4.3. LVDS SERDES Receiver Modes
4.1. LVDS SERDES Receiver Blocks x
4.1.1. Dynamic Phase Alignment Block 4.1.2. Synchronizer (DPA FIFO) 4.1.3. Data Realignment Block (Bit Slip) 4.1.4. Deserializer
4.3. LVDS SERDES Receiver Modes x
4.3.1. Non-DPA Mode 4.3.2. DPA Mode 4.3.3. Soft-CDR Mode
5. Intel Agilex® 7 M-Series High-Speed SERDES Design Guidelines x
5.1. Use PLLs in Integer PLL Mode for LVDS 5.2. Use High-Speed Clock from PLL to Clock SERDES Only 5.3. Pin Placement for Differential Channels 5.4. SERDES Pin Pairs for Soft-CDR Mode 5.5. Placing LVDS Transmitters and Receivers in the Same GPIO-B Sub-Bank 5.6. VCCIO_PIO Power Scheme for LVDS SERDES
1. Intel Agilex® 7 M-Series LVDS SERDES Overview
2. Intel Agilex® 7 M-Series High-Speed SERDES Architecture
3. Intel Agilex® 7 M-Series LVDS SERDES Transmitter
4. Intel Agilex® 7 M-Series LVDS SERDES Receiver
5. Intel Agilex® 7 M-Series High-Speed SERDES Design Guidelines
6. Documentation Related to the Intel Agilex® 7 LVDS SERDES User Guide: M-Series
7. Document Revision History for the Intel Agilex® 7 LVDS SERDES User Guide: M-Series

4.3. LVDS SERDES Receiver Modes

M-Series devices support three receiver modes.
  • Non-DPA mode
  • DPA mode
  • Soft-CDR mode

Section Content
Non-DPA Mode
DPA Mode
Soft-CDR Mode

Level Two Title

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