F-tile Architecture and PMA and FEC Direct PHY IP User Guide

ID 683872
Date 4/03/2023

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Document Table of Contents FGT Receiver Buffer and Equalizer

A simplified FGT receiver analog front end is shown in the following figure.
Figure 47. Simplified RX Analog Front End
The various capacitors and resistors for the receiver analog front end are described below:
  1. You can implement on board AC coupling capacitors, Con-board, based on applicable standards. For example, PCIe requires 176nF to 265nF on board AC coupling capacitors.
  2. Con-chip, on-chip AC coupling capacitor is 1pF. It is always on and is only bypassed in SDI mode.
  3. RDIFF-DC, DC differential receive impedance is 50Ω single ended. It is programmable to 85Ω or 100Ω.
  4. When you implement on-board AC coupling capacitors you must set VRX-CM-DC to ground termination. When it is DC coupled and no on-board AC coupling capacitors are implemented, VRX-CM-DC, receiver input DC common-mode voltage at the bumps must be:
    1. Smaller than 700mV, if squelch detect is not used.
    2. Must be between 200mV to 300mV, if squelch detect is used.
    Vcm is set to 700mV automatically if you use SDI mode.

The receiver buffer and equalizer function the same for FHT and FGT PMAs. See FHT Receiver Buffer and Equalizer for details.