F-tile Architecture and PMA and FEC Direct PHY IP User Guide

ID 683872
Date 4/03/2023

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5.4.2. FHT PMA Registers Access Example

An example of using the F-Tile Global Avalon® Memory-Mapped Interface Intel® FPGA IP to access the FHT PMA registers is shown below.
To read the FHT loopback setting registers:
  1. Write 0x10 to register 0xffffc.
  2. For lane 0, read register 0x45800.
  3. For lane 1, read register 0x4D800.
  4. For lane 2, read register 0x55800.
  5. For lane 3, read register 0x5D800.