3.13. Configuring the F-Tile PMA/FEC Direct PHY Intel® FPGA IP for Hardware Testing
This section details the steps you should follow to configure the F-Tile PMA/FEC Direct PHY Intel® FPGA IP in order to bring-up the FHT or FGT PMA for hardware testing using System Console in the Intel® Quartus® Prime software. You can configure the PMA analog settings to enable functions such as serial loopback, PRBS generators and checkers, to modify TX equalizer settings, and BER measurements.
You can choose either of the following methods to access the PMA registers via JTAG using System Console:
- Using the Debug Endpoint Avalon® interface within the F-Tile PMA/FEC Direct PHY Intel® FPGA IP .
- Using JTAG to Avalon Master Bridge Intel FPGA IP instantiated from the IP Catalog.