126.96.36.199.3. FHT Deserializer
The deserializer clocks in serial input data from the receiver buffer using the high-speed serial recovered clock, and deserializes the data using the low-speed parallel recovered clock. The deserializer forwards the deserialized data to the receiver PCS or FPGA core. The deserializer supports the following deserialization factors: 32, 64, and 128.