F-tile Architecture and PMA and FEC Direct PHY IP User Guide

ID 683872
Date 4/03/2023

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Document Table of Contents

5.1. IP Parameters

Table 95.   F-Tile Global Avalon® Memory-Mapped Interface Intel® FPGA IP Parameters
Parameter Values Description
Enable read_datavalid port On/Off When enabled (On), port readdatavalid is added to indicate when readdata is available, make the interface compatible with pipelined read bus host. No throughput improvement by enabling it. The default value is Off.
Message level for rule violations



Specifies the messaging level to use for parameter rule violations. Selecting error causes all rule violations to prevent IP generation. Selecting warning displays all rule violations as warnings and allows IP generation in spite of violations. The default value is error.

Enable Debug Master Endpoint on Global AVMM


When enabled (On), the F-Tile Global Avalon® Memory-Mapped Interface Intel® FPGA IP uses an embedded Native PHY Debug Master Endpoint that connects internally to the Avalon® memory-mapped slave interface. It can access the global Avalon® memory-mapped space of the tile instead of the user interface. It can perform certain test and debug functions through JTAG using System Console.
Note: The user Avalon® memory-mapped interface interface is unavailable when you enable this parameter and only clock and reset inputs are present.
The default value is Off.