F-tile Architecture and PMA and FEC Direct PHY IP User Guide

ID 683872
Date 4/03/2023

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Document Table of Contents

2.1.11. Reconfiguration Interfaces

Each EMIB has one datapath Avalon® memory-mapped interface and one PMA Avalon® memory-mapped interface, and each F-tile has one global Avalon® memory-mapped interface.
  • The datapath Avalon® memory-mapped interface can access 400G hard IP (MAC, PCS, and FEC), 200G hard IP (PCS and FEC), EMIBs (both tile and core sides), PMA interfaces, and control and status registers (CSRs) implemented in the FPGA core.
  • The PMA Avalon® memory-mapped interface can access PCIe* hard IP and PMAs.
  • The global Avalon® memory-mapped interface can access all F-tile components: the tile side of the EMIBs, 400G hard IP, 200G hard IP, PCIe* hard IP, PMA interfaces, PMAs, and the tile FIFO interface. It cannot access the core side of the EMIBs (including the core FIFO interface) because that side of the EMIBs is in the FPGA core.
Figure 9. F-Tile Architecture Building Blocks with Reconfiguration Interfaces
Figure 10. Tile-to-FPGA-Core Interfaces

There is one reconfig_pdp per hard IP instance and one reconfig_xcvr per PMA. reconfig_pdp provides the parallel datapath interface of both 400G hard IP and 200G hard IP access to the datapath Avalon® memory-mapped interface. reconfig_pdp is specific to Direct PHY IP. Other interfaces may use different naming. Ethernet, for example, uses reconfig_eth.

For Ethernet with PCS 64b/66b backplane scrambled coding enabled, the global Avalon® memory-mapped interface IP is part of the hard IP. So, if you instantiate a global Avalon® memory-mapped interface IP and the Ethernet hard IP instantiates an additional global Avalon® memory-mapped interface IP internally, an auto-inserted arbiter arbitrates between the two.