3.3.1. General and Common Datapath Options
You can customize your instance of the F-Tile PMA/FEC Direct PHY Intel® FPGA IP by specifying parameter values to suit your application. The parameters are organized in the following sections for each functional block and feature:
- General and Common Datapath options
- TX Datapath Options
- RX Datapath Options
- RS-FEC (Reed Solomon Forward Error Correction) Options
- Avalon Memory Mapped Interface Options
|Number of system copies||1-16||
Specifies the total number of independent system copies.
For example, you can create multiple copies of the same PMA/FEC mode configuration by setting this to value of 2 (or more) and with the same PMA configuration. This is duplicated to create 2 PMA lanes of the same configuration for the given example. Default value is 1.
|Common Datapath Options|
|Specifies the type of PMA used. FGT PMA can operate up to 58.125Gbps PMA. FHT PMA can operate up to 116Gbps. Default is FGT.|
|FGT PMA configuration rules||
Basic,OTN, CPRI, GPON, SDI, SONET, SATA, USB
|Selects the protocol configuration rules for the FGT PMA. This parameter governs the rules for correct settings of individual parameters within the PMA. Certain features of the PMA are available only for specific protocol configuration rules. This parameter is not a preset. You must still correctly set all other parameters for your specific protocol and application needs.|
|Number of PMA lanes||1, 2, 4, 6, 8, 12, 16||Specifies the total number of PMA lanes in a bonded group. For example, if the value is 4, this means there are 4 PMA lanes bonded in the same group and share the same bonding clock. A value of 1 means there is no System bonding. Values 6 and 12 supported only for PMA Direct mode. Default value is 1.|
|Datapath clocking mode||
|Specifies whether the PMA parallel clock or System PLL is used to clock the TX/RX datapath. Use of System PLL is required when Enable RS-FEC is on or dynamic reconfiguration is intended. Default value is System PLL.|
|System PLL frequency||31.25 to 1000||Specifies the System PLL clock frequency (MHz) and applicable if datapath clocking mode is selected as System PLL. Default value is 830.08 24.|
|Specifies the PMA operation mode. TX simplex and RX simplex can operate at independent rates. Default value is Duplex.|
|PMA modulation type||PAM4,NRZ||Specifies the modulation type used for serial data. Default value is PAM4.|
PMA data rate
|25781.25||Specifies the PMA data rate in units of Mbps (megabits per second). Default value is 25781.25.|
|PMA parallel clock frequency||Data rate / PMA Width||Displays PMA parallel clock frequency which is PMA data rate divided by PMA interface width in MHz. Default value is Data rate / PMA Width. The PMA parallel clock frequency applies to both the Word Clock and Bond Clock.|
|PMA width||8, 10, 16, 20, 32, 64, 128||Specifies the PMA data width. 128-bit is only supported for FHT. The PMA data width specifies the total number of PMA bond streams (PMA bonding). For example:
|Enable RX de-skew when available||On/Off||Enables the RX de-skew feature. This feature is only available in:
|Enable simplified TX data interface||On/Off||Enables simplified data and control interface between the FPGA and PMA for SATA and USB protocol modes. When the FGT PMA configuration rules parameter is set to SATA or USB, you can enable this option to control the fgt_tx_pma_elecidle port. Refer to TX PMA Control Signals for more information.|
|Provide separate interface for each PMA||On/Off||
When On, the PMA/FEC Direct PHY IP presents separate data and clock interfaces for each PMA lane, rather than a wide bus.
Default value is Off. Refer to Signal and Port Reference for a list of signals that are not impacted by this feature.
Note: When the Enable RS-FEC option is on, a separate interface is not available for each PMA by use of the Provide separate interface for each PMA option.