F-tile Architecture and PMA and FEC Direct PHY IP User Guide

ID 683872
Date 4/03/2023

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2.1.4. FEC Architecture

Each 400G hard IP and 200G hard IP fracture includes FEC. The FEC block is located between the PCS and PMA interface blocks of a fracture.

  • Four adjacent st_x1 fractures or two adjacent st_x2 fractures share the same clock and are grouped together as a FEC core.
  • st_x4 uses one FEC core.
  • Two or four FEC cores are grouped together in st_x8 and st_x16 fractures, respectively.

There is a total of four FEC cores in 400G hard IP and two FEC cores in 200G hard IP. Each FEC core can be used to implement multiple FEC modes as shown in the following table.

Table 7.  F-Tile Supported FEC Modes and Compliance Specifications
FEC Mode Specification FEC Compliance Specification Example Protocols
Firecode IEEE IEEE 802.3 BASE-R Firecode (CL 74) 25GbE-1 IEEE BASE-R
RS(272, 258) LL ETC ETC RS(272,258) 50GbE-1, 100GbE-2, 200GbE-4, 400GbE-8 ETC
RS(528, 514) KR IEEE IEEE 802.3 RS(528, 514) (CL 91) 25GbE-1
ETC IEEE 802.3 RS(528, 514) (CL 91) ETC 25GbE-1, 50GbE-2 ETC
Fibre Channel Fibre Channel RS(528, 514)

Fibre Channel 16G, 32G, 64G and 128G

CPRI 10.1376 Gbps and 24.33024 Gbps

FlexO FlexO RS(528, 514)


100G FlexO

RS(544, 514) KP IEEE IEEE 802.3 RS(544,514) (CL 134)


100GbE-1, 100GbE-2


400GbE-4, 400GbE-8


Custom Custom IEEE 802.3 RS(544, 514) (CL 134) at 26.5625 Gbps NRZ





Interlaken Interlaken RS(544, 514) Interlaken (100G bundles)
Fibre Channel Fibre Channel RS(544, 514) 16G, 32G, and 128G Fibre Channel
FlexO FlexO RS(544, 514) 100G FlexO (4x 25G NRZ, 2x 50G PAM4, 1x 100G PAM4)
Note: The table above has a few examples of the list of protocols supported by F-tile. The list is not an exhaustive list of protocols supported.

If your configuration has multiple interface in one FEC core, you need custom cadence. Refer to Datapath Clock Cadences for details. Refer to FEC Placement Rules for examples.