F-tile Architecture and PMA and FEC Direct PHY IP User Guide

ID 683872
Date 4/03/2023
Public

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5.4.5. 200G MAC/PCS Interface Registers Access Example

The 200G MAC/PCS interface registers are a part of the F-Tile Ethernet Intel FPGA Hard IP register map.
For a design where multiple IP instances are accessed by a single F-Tile Global Avalon® Memory-Mapped Interface Intel® FPGA IP, you need to use the corresponding base address to access the separate IP instances. The following table shows base address for each Ethernet mode.
Note: For the F-Tile PMA/FEC Direct PHY Intel® FPGA IP, there is no PCS or MAC utilized, hence there is no need to access the 200G MAC/PCS registers. For other protocol IPs where the MAC or PCS is used, you can access the 200G MAC/PCS registers.
Table 101.  200G MAC/PCS Base Address for Global Avalon® Memory-Mapped Access
Ethernet Mode Base Address (Byte Address)
25GE_0 0x0000
50GE_0 0x1000
100GE_0 0x2000
200GE_0 0x3000
25GE_1 0x4000
25GE_2 0x5000
50GE_1 0x6000
25GE_3 0x7000
25GE_4 0x8000
50GE_2 0x9000
100GE_1 0xA000
25GE_5 0xB000
25GE_6 0xC000
50GE_3 0xD000
25GE_7 0xE000
Note: The table is only applicable for global Avalon® memory-mapped interface access. For local Avalon® memory-mapped interface access, refer to Ethernet Avalon® Memory-Mapped Interface Address Space in the F-Tile Ethernet Intel FPGA Hard IP User Guide.
As an example, if a design has four IPs instantiated and accessed by a single F-Tile Global Avalon® Memory-Mapped Interface Intel® FPGA IP, where:
  • The first IP is a 1x50Gbps module; placed in stream0 and stream1, fracture st_x2_0, Ethernet mode 50GE_0
  • The second IP is a 2x50Gbps module; placed in stream4 to stream7, fracture st_x4_1, Ethernet mode 100GE_1
  • The third IP is a 1x25Gbps module; placed in stream2, fracture st_x1_2, Ethernet mode 25GE_2
  • The fourth IP is a 1x25Gbps module; placed in stream3, fracture st_x1_3, Ethernet mode 25GE_3
Note: Use the F-Tile Channel Placement Tool to find out where each IP module is placed; in which streams, what fracture type, and refer to the Fracture Type and Ethernet Mode Mapping table to determine the Ethernet mode.
To read the TX MAC max TX frame size register:
  1. Write register 0xffffc with value 0x6.
  2. Read the following registers for the TX MAC max TX frame size register value:
    1. For the first IP instance, read register 0x1208.
    2. For the second IP instance, read register 0xA208.
    3. For the third IP instance, read register 0x5208.
    4. For the fourth IP instance, read register 0x7208.