F-tile Architecture and PMA and FEC Direct PHY IP User Guide
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Visible to Intel only — GUID: fkx1678307836730
Ixiasoft
Visible to Intel only — GUID: fkx1678307836730
Ixiasoft
3.11.6.2. Accessing FHT PMA Registers
- For the channel on lane 0: offset address
- For the channel on lane 1: offset address + 0x8000
- For the channel on lane 2: offset address + 0x10000
- For the channel on lane 3: offset address + 0x18000
For FHT PMA registers with offset address greater than 0x48000 and smaller than 0xFFFFC, you can directly use the offset address provided in the F-Tile PMA/FEC Direct PHY Intel® FPGA IP register map.
- For the channel 0: 0xFFFFC
- For the channel 1: 0x1FFFFC
- For the channel 2: 0x2FFFFC
- For the channel 3: 0x3FFFFC