F-tile Architecture and PMA and FEC Direct PHY IP User Guide

ID 683872
Date 4/03/2023

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5.4.3. 400G MAC/PCS Interface Registers Access Example

The 400G MAC/PCS interface registers are a part of the F-Tile Ethernet Intel FPGA Hard IP register map.
For a design where multiple IP instances are accessed by a single F-Tile Global Avalon® Memory-Mapped Interface Intel® FPGA IP, you need to use the corresponding base address to access the separate IP instances. The following table shows base address for each Ethernet mode.
Note: For the F-Tile PMA/FEC Direct PHY Intel® FPGA IP, there is no PCS or MAC utilized, hence there is no need to access the 400G MAC/PCS registers. For other protocol IPs where the MAC or PCS is used, you can access the 400G MAC/PCS registers.
Table 99.  400G MAC/PCS Base Address for Global Avalon® Memory-Mapped Access
Ethernet Mode Base Address (Byte Address)
25GE_0 0x00000
50GE_0 0x01000
100GE_0 0x02000
200GE_0 0x03000
400GE_0 0x04000
25GE_1 0x05000
25GE_2 0x06000
50GE_1 0x07000
25GE_3 0x08000
25GE_4 0x09000
50GE_2 0x0A000
100GE_1 0x0B000
25GE_5 0x0C000
25GE_6 0x0D000
50GE_3 0x0E000
25GE_7 0x0F000
25GE_8 0x10000
50GE_4 0x11000
100GE_2 0x12000
200GE_1 0x13000
25GE_9 0x14000
25GE_10 0x15000
50GE_5 0x16000
25GE_11 0x17000
25GE_12 0x18000
50GE_6 0x19000
100GE_3 0x1A000
25GE_13 0x1B000
25GE_14 0x1C000
50GE_7 0x1D000
25GE_15 0x1E000
Note: The table is only applicable for global Avalon® memory-mapped interface access. For local Avalon® memory-mapped interface access, refer to Ethernet Avalon® Memory-Mapped Interface Address Space in the F-Tile Ethernet Intel FPGA Hard IP User Guide.
As an example, if a design has four IPs instantiated and accessed by a single F-Tile Global Avalon® Memory-Mapped Interface Intel® FPGA IP, where:
  • The first IP is a 1x25Gbps module; placed in stream0, fracture st_x1_0, Ethernet mode 25GE_0
  • The second IP is a 2x25Gbps module; placed in stream2 and stream3, fracture st_x2_1, Ethernet mode 50GE_1
  • The third IP is a 1x50Gbps module; placed in stream4 and stream5, fracture st_x2_2, Ethernet mode 50GE_2
  • The fourth IP is a 4x25Gbps module; placed in stream8 to stream11, fracture st_x4_2, Ethernet mode 100GE_2
Note: Use the F-Tile Channel Placement Tool to find out where each IP module is placed; in which streams, what fracture type, and refer to the Fracture Type and Ethernet Mode Mapping table to determine the Ethernet mode.
To read the RX PCS status register:
  1. Write register 0xffffc with value 0x2
  2. Read the following registers for the RX PCS status register value:
    1. For the first IP instance, read register 0x0084
    2. For the second IP instance, read register 0x7084
    3. For the third IP instance, read register 0xA084
    4. For the fourth IP instance, read register 0x12084