F-tile Architecture and PMA and FEC Direct PHY IP User Guide

ID 683872
Date 4/03/2023
Public

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5.3. Hardware Flow Using the F-Tile Global Avalon® Memory-Mapped Interface Intel® FPGA IP

You can access the FHT and FGT PMA registers using the F-Tile Global Avalon® Memory-Mapped Interface Intel® FPGA IP.

You can access the F-Tile Global Avalon® Memory-Mapped Interface Intel® FPGA IP by using the Enable Debug Master Endpoint on Global AVMM parameter, JTAG to Avalon® Master Bridge Intel FPGA IP, Nios® II Gen 2 processor, or customized state machines. The rest of this section uses the JTAG to Avalon® Master Bridge Intel FPGA IP as an example to demonstrate the steps to add the F-Tile Global Avalon® Memory-Mapped Interface Intel® FPGA IP to work with a F-Tile PMA/FEC Direct PHY Intel® FPGA IP design.

  1. Add the F-Tile Global Avalon® Memory-Mapped Interface Intel® FPGA IP into your design and enable the read_data_valid port as shown in the following figures.
    Note: Enabling the Enable Debug Master Endpoint on Global AVMM parameter is optional. When enabled, an embedded Native PHY Debug Master Endpoint is implemented internally and you can skip steps 2 and 3.
    Figure 92. F-Tile Global Avalon Memory-Mapped Interface Intel FPGA IP
    Figure 93.  F-Tile Global Avalon® Memory-Mapped Interface Intel® FPGA IP Settings
  2. Add the JTAG to Avalon® Master Bridge Intel FPGA IP into your design.
    Figure 94. JTAG to Avalon® Master Bridge Intel FPGA IP
  3. Declare wires to connect the g_avmm interface to the jtag_master ports as shown in the following figure.
    Note: The g_avmm_address port of g_avmm interface is 18 bits and the master_address port of jtag_master is 32 bits.
    Note: You need to enable the readdatavalid port in the JTAG to Avalon® Master Bridge Intel FPGA IP and connect it to the corresponding F-Tile Global Avalon® Memory-Mapped Interface Intel® FPGA IP port.
    Figure 95.  F-Tile Global Avalon® Memory-Mapped Interface Intel® FPGA IP to JTAG to Avalon® Master Bridge Intel FPGA IP RTL Connections
  4. In the Intel® Quartus® Prime Pro Edition software compilation flow, the F-Tile Global Avalon® Memory-Mapped Interface Intel® FPGA IP instance has to be associated with the F-Tile PMA/FEC Direct PHY Intel® FPGA IP instance using the IP_COLOCATE qsf assignment as shown below.
    set_instance_assignment -name IP_COLOCATE F_TILE -from <GAVMM IP Instance Path> -to <F-tile DPHY IP Instance Path> -entity <Top-Level Entity>
    To create the qsf assignments you must perform the following steps:
    1. Run the Support-Logic Generation for your design in the Intel® Quartus® Prime Pro Edition software.
      Figure 96. Support Logic Generation Intel® Quartus® Prime Pro Edition Software
      Note: A Logic Generation failure is expected since the qsf assignments are not defined yet.
      Figure 97. Logic Generation Failure in Intel® Quartus® Prime Pro Edition Software
    2. Click on the compilation report next to the Logic Generation button and navigate to the IP Parameter Settings Report, Pre Placement report under Logic Generation Tool report folder as shown below:
      Tip: You can use the Logic Generation Tool report during your debug to check values of the parameters. This report lists the available parameters that you may use to explore alternate solutions.
      Figure 98. Logic Generation Reports in Intel® Quartus® Prime Pro Edition Software
    3. Identify the F-Tile Global Avalon® Memory-Mapped Interface Intel® FPGA IP and F-Tile PMA/FEC Direct PHY Intel® FPGA IP instance paths.
      Note: F-Tile Global Avalon® Memory-Mapped Interface Intel® FPGA IP instance path ends with gavmm_f_0 and the F-Tile PMA/FEC Direct PHY Intel® FPGA IP instance path ends with directphy_f_0.
    4. Add the IP_COLOCATE assignment in your Intel® Quartus® Prime Pro Edition software qsf file. As an example, you would add the following assignments in your qsf file for the instance report shown above.
      set_instance_assignment -name IP_COLOCATE F_TILE -from Tile1_top|gavmm_inst1|gavmm_f_0 -to Tile1_top|DPHY1|directphy_f_0 -entity multi_tile_demo
      set_instance_assignment -name IP_COLOCATE F_TILE -from Tile1_top|gavmm_inst1|gavmm_f_0 -to Tile1_top|DPHY2|directphy_f_0 -entity multi_tile_demo
      set_instance_assignment -name IP_COLOCATE F_TILE -from Tile2_top|gavmm_inst2|gavmm_f_0 -to Tile2_top|DPHY3|directphy_f_0 -entity multi_tile_demo
      This example is a multi-tile design with the top level named multi_tile_demo. The design has three instances of F-Tile PMA/FEC Direct PHY Intel® FPGA IP named DPHY1, DPHY2 and DPHY3 and two instances of F-Tile Global Avalon® Memory-Mapped Interface Intel® FPGA IP named gavmm_inst1 and gavmm_inst2. The DPHY1 and DPHY2 instances are placed in the same F-Tile and are accessed using gavmm_inst1 (1st and 2nd qsf assignments). The DPHY3 is placed in another F-Tile and is accessed using gavmm_inst2 (3rd qsf assignment).
    5. Once you have added the IP_COLOCATE qsf assignments to your design, it should compile successfully.
  5. To perform hardware testing to access registers using the global Avalon® interface you need to do the following:
    1. Write the page address of the block you want to access to the page address register: 0xffffc. The following table shows the page address of the various blocks in the F-tile.
      Table 97.  Block and Page Address
      Block Page Address
      EMIB 0x00
      400G MAC/PCS Interface 0x02
      400G FEC/PMA Interface 0x04
      200G MAC/PCS Interface 0x06
      200G FEC/PMA Interface 0x08
      PCIe Hard IP 0x0A
      FGT PMA Quad 0 0x0C
      FGT PMA Quad 1 0x0D
      FGT PMA Quad 2 0x0E
      FGT PMA Quad 3 0x0F
      FHT PMA 0x10
    2. You can then read and write values to the PMA offset register address to access the registers.