4.5. Guidelines to Indicate all System PLL Reference Clocks are Ready
When the system PLL #N (N = 0, 1, 2) mode is enabled but the reference clock is not available or stable at device programming time, you must set the Refclk is available at device configuration parameter to Off. When the system PLL #N (N = 0, 1, 2) mode is disabled, you can ignore the reference clock.
For all enabled system PLLs that have the parameter Refclk is available at device configuration set to On, you must provide stable reference clocks for the system PLLs at device programming time.
For all enabled system PLLs that have the parameter Refclk is available at device configuration set to Off, system PLL does not start locking until you perform the Global Avalon® memory-mapped interface write operations signaling that all reference clocks are ready.
When Refclk is available at device configuration parameter is set to Off, an internal clock is used to calibrate and configure the FPGA device. Due to the low frequency of the internal clock, the calibration and configuration takes longer to finish. In addition, after the system PLL reference clock is ready, you need to use global Avalon® memory-mapped interface to write to specific registers. This flow may not meet the link up requirements for some IP protocols. You must make sure your design application is compatible with this flow. Intel recommends supplying a stable and running system PLL reference clock at device programming, and enabling the Refclk is available at device configuration feature.
For PCIe* interfaces that require compliance to PCIe* link training specifications, the reference clock to the system PLL must be available and stable before device configuration begins. You must set the Refclk is available at device configuration parameter in the system PLL IP to On and drive the reference clock from an independent and free running clock source. Alternately, if the reference clock from the PCIe* link is guaranteed to be available before device configuration begins, you may use it to drive the system PLL. Once the PCIe* link refclk is alive, it must never go down.