1. Intel® MAX® 10 High-Speed LVDS I/O Overview 2. Intel® MAX® 10 High-Speed LVDS Architecture and Features 3. Intel® MAX® 10 LVDS Transmitter Design 4. Intel® MAX® 10 LVDS Receiver Design 5. Intel® MAX® 10 LVDS Transmitter and Receiver Design 6. Intel® MAX® 10 High-Speed LVDS Board Design Considerations 7. Soft LVDS Intel® FPGA IP Core References 8. Intel® MAX® 10 High-Speed LVDS I/O User Guide Archives 9. Document Revision History for Intel® MAX® 10 High-Speed LVDS I/O User Guide
5.2.1. LVDS Transmitter and Receiver PLL Sharing Implementation
In applications where an LVDS transmitter and receiver are required, you typically need two PLLs—one for each interface. Using the Soft LVDS IP core, you can reduce PLL usage by sharing one PLL between the transmitter and receiver.
- Turn on the Use common PLL(s) for receivers and transmitters option to allow the Intel® Quartus® Prime compiler to share the same PLL.
- To share a PLL, several PLLs must have the same PLL settings, such as PLL feedback mode, clock frequency, and phase settings. The LVDS transmitters and receivers must use the same input clock frequency and reset input.
- If you are sharing a PLL, you can use more counters to enable different deserialization factor and data rates for the transmitters and receivers. However, because you are using more PLL counters, the PLL input clock frequency and the PLL counter resolution cause limitations in clocking the transmitters and receivers.
Note: The number of PLLs available differs among Intel® MAX® 10 packages. Intel recommends that you select a Intel® MAX® 10 device package that provides sufficient number of PLL clockouts for your design.