Intel® MAX® 10 High-Speed LVDS I/O User Guide

ID 683760
Date 10/31/2022
Document Table of Contents

4.2.5. HiSpi Receiver External Termination

The HiSpi receiver requires a single-resistor external termination scheme.
Figure 21. External Termination for HiSpi Receiver

Did you find the information on this page useful?

Characters remaining:

Feedback Message