1. Intel® MAX® 10 High-Speed LVDS I/O Overview 2. Intel® MAX® 10 High-Speed LVDS Architecture and Features 3. Intel® MAX® 10 LVDS Transmitter Design 4. Intel® MAX® 10 LVDS Receiver Design 5. Intel® MAX® 10 LVDS Transmitter and Receiver Design 6. Intel® MAX® 10 High-Speed LVDS Board Design Considerations 7. Soft LVDS Intel® FPGA IP Core References 8. Intel® MAX® 10 High-Speed LVDS I/O User Guide Archives 9. Document Revision History for Intel® MAX® 10 High-Speed LVDS I/O User Guide
6.1. Guidelines: Improve Signal Quality
To improve signal quality, follow these board design guidelines:
- Base your board designs on controlled differential impedance. Calculate and compare all parameters such as trace width, trace thickness, and the distance between two differential traces.
- Maintain equal distance between traces in differential I/O standard pairs as much as possible. Routing the pair of traces close to each other maximizes the common-mode rejection ratio (CMRR).
- Keep the traces as short as possible to limit signal integrity issues. Longer traces have more inductance and capacitance.
- Place termination resistors as close to receiver input pins as possible.
- Use surface mount components.
- Avoid 90° corners on board traces.
- Use high-performance connectors.
- Design backplane and card traces so that trace impedance matches the impedance of the connector and termination.
- Keep an equal number of vias for both signal traces.
- Create equal trace lengths to avoid skew between signals. Unequal trace lengths result in misplaced crossing points and decrease system margins as the transmitter-channel-to-channel skew (TCCS) value increases.
- Limit vias because they cause discontinuities.
- Keep toggling single-ended I/O signals away from differential signals to avoid possible noise coupling.
- Do not route single-ended I/O clock signals to layers adjacent to differential signals.
- Analyze system-level signals.